Papers by Keyword: Metal Gate

Abstract: Tungsten importance in semiconductor manufacturing is renewed more and more due to its usage not only as metallization for plugs, but also in metal gates architectures. As the scaling down of the devices is becoming aggressive, the metal interfaces become more critical. Hence, a deeper understanding of the evolution of the W surface after wet cleaning processes is becoming increasingly more important.

Abstract: An all-wet process based on a novel chemistry has been developed to enable the removal of high-dose implanted photoresist in the presence of exposed metal layers and other materials typical of advanced gate stacks.

Abstract: HfTaO-based MOS capacitors with different top electrode (Ag、Au、Pt) were successfully fabricated by dual ion beam sputtering deposition (DIBSD). We presented the effect of different metal gate on the capacity, flat band voltage shift, leakage current and conduction mechanism. It has been found that the Pt-electrode capacitor exhibited the highest accumulation capacitance. In addition, the largest hysteresis loop in Pt/HfTaO/Si capacitor during the forward-and-reverse voltage sweeping from +2.5V to -2.5V was observed. The result indicates the presence of a large amount of fixed charges or oxygen vacancies exist in interface Pt/HfTaO, which is consistent with the prediction from Qf results. It is proved that even though E_ot of the Pt-electrode capacitor is lower than that of the Ag, Au-electroded, and that of leakage current still has the smallest value at a high electric field due to Pt with a high enough work function Φ_ms(Pt)=5.65eV.

Abstract: As semiconductor technology moves past the 32nm CMOS node, material loss becomes an ever more important topic. Besides impacting the size of physical features, material loss impacts electrical results, process control, and defectivity. The challenge this poses is further exacerbated by the introduction of new materials. The largest single influx of new materials has come over the last decade with the introduction of high-k/metal gate (HK/MG) materials. This paper focuses on the front-end-of-line (FEOL), summarizing key materials loss issues by process loop.

Abstract: High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.

Abstract: In this work the removal of different metallic and particulate contaminants relevant for high-k/metal gate processing is studied. Best cleaning efficiency of both silicon and nitride substrates is achieved using a HF/HNO3-based cleaning resulting in a particle removal efficiency higher than 90% and metal removal down to 1010 at/cm2.