Design of Quaternary Half Adder Using Hybrid SETMOS Cell

Abstract:

Adder is one of the important arithmetic units in computers. In this paper, we investigate the implementation of quaternary half adder based on multiple-valued (MV) logic gates using single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. We use hybrid SETMOS universal literal gate which has been proposed by Mahapatra and Ionesco. We apply two 4-radix inputs to the proposed quaternary half adder and obtain sum and carry outputs. The logic operation of the proposed quaternary half adder is verified by using HSPICE simulator. Moreover we compare the performance of our proposed quaternary half adder with the performance of a quaternary half adder based on MOS technology.

• Periodical: Applied Mechanics and Materials (Volumes 110-116)
• Pages: 5085-5089
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.110-116.5085
• Online since: October 2011
• Authors: Khadijeh Feizi, Ali Shahhoseini
• Keywords: Multiple Valued Logic, Quaternary Half Adder, Single Electron Transistor, Universal Literal Gate

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