Specific hardware solutions are always faster than programmable architectures. But dedicated architectures have the inherent disadvantage of inflexibility. Changes in the algorithm or extensions of the application are handled easily by programmable architectures. The approach discussed here involves a hardware-software co-design to optimize on performance and programmability. The architecture houses two SHARC processors to aid in parallelizing the image processing algorithms, and a reconfigurable FPGA which may be configured on the fly to execute any of the real-time algorithms as desired. The functional memory would consist of pre-designs (FPGA based) of certain objects, each of which could be used to configure an FPGA to perform a particular function.