[1]
Zhengfeng Huang, Huaguo Liang, A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies, " Proc. IEEE Int, l On-Line Testing Symp. , 2008, pp.175-176.
DOI: 10.1109/iolts.2008.9
Google Scholar
[2]
Q. Zhou, K. Mohanram, Gate Sizing to Radiation Harden Combinational logic, IEEE Trans. CAD, vol. 25, no. 1, 2006, pp.155-166.
DOI: 10.1109/tcad.2005.853696
Google Scholar
[3]
S. Mitra, N. Seifert, M. Zhang, et al, Robust System Design with Built-In Soft-Error Resilience , IEEE Trans. Computer, vol. 38, no. 2, Feb. 2005, pp.43-52.
DOI: 10.1109/mc.2005.70
Google Scholar
[4]
K. Reick, P.N. Sanda, S. Swaney, et al, Fault-tolerant Design of the IBM Power6 Microprocessor, IEEE Tran. Micro, vol. 28, no. 2, 2008, pp.30-38.
DOI: 10.1109/mm.2008.22
Google Scholar
[5]
S.S. Mukherjee,M. Kontz S.K. Reinhardt, Detailed Design and Evaluation of Redundant Multi-Threading Alternatives, Proc. Intl. Symp. Computer Architecture, 2002, pp.99-110.
DOI: 10.1109/isca.2002.1003566
Google Scholar
[6]
Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery , " Proc. IEEE/IFIP Int, l Conf. Dependable Systems and Networks, 2007, pp.256-265.
DOI: 10.1109/dsn.2007.5
Google Scholar
[7]
M. Nicolaidis, Design for soft error mitigation, IEEE Trans. Device and Materials Reliability, vol. 5, no. 3, 2005, pp.405-418.
DOI: 10.1109/tdmr.2005.855790
Google Scholar
[8]
N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective. Addison Wesley, (2004).
Google Scholar
[9]
E. L. Hill, M. H. Lipasti, and K. K. Saluja, An accurate flip-flop selection technique for reducing logic SER, " Proc. Int, l Conf. Dependable Systems and Networks, 2008: 128-136.
DOI: 10.1109/dsn.2008.4630081
Google Scholar
[10]
http: /www. eas. asu. edu/~ptm.
Google Scholar
[11]
G. C. Messenger, Collection of Charge on Junction Nodes from Ion Tracks, IEEE Trans. Nuclear Science, vol. 29, no. 6, 1982, p.2024-(2031).
DOI: 10.1109/tns.1982.4336490
Google Scholar
[12]
D. Bull, S. Das, K. Shivashankar, et al, A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation, IEEE Journal of Solid State Circuits, vol. 46, no. 1, 2011, pp.18-31.
DOI: 10.1109/jssc.2010.2079410
Google Scholar