A 6-Bit 5GS/s Pseudo-Thermometer Segmented CMOS DAC

Wen Yuan Li; Yi Jun Song

doi:10.4028/www.scientific.net/AMM.513-517.4585

Paper Titles

Research on Indirect Charging Radio Frequency Explosive Magnetic Flux Compression Generator
p.4567

A 8GHz Differential Comparator for Ultra High Speed ADC in 90nm CMOS Technology
p.4572

Design of a Low Power Multi-Channel 10Bit SAR ADC
p.4576

A Low Power SiGe-BiCMOS LNA for COMPASS Applications
p.4580

A 6-Bit 5GS/s Pseudo-Thermometer Segmented CMOS DAC
p.4585

A Temperature Compensation Circuit within Constant Current Charging Cycle
p.4589

Numerical Simulation and Experimental Study of Inner Flow Field in Marine Centrifugal Pump
p.4593

Patent Analysis of the Rare Earth Extracting Separation Technology
p.4597

Research on the Transformation of Ba-Construction in Patent Machine Translation
p.4601

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 513-517A 6-Bit 5GS/s Pseudo-Thermometer Segmented CMOS...

A 6-Bit 5GS/s Pseudo-Thermometer Segmented CMOS DAC

Abstract:

In order to keep pace with the development of gigabits per second (Gbps) wireless communication and make the promising 60GHz band millimeter wave communication a reality, design of a DAC available to operate in the GS/s becomes a bottleneck problem. A 6-bit 5GS/s, power-efficient DAC is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floorplannings and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted. Post simulation results shows DNL errors and INL errors of the DAC can be controlled within±0.23LSB and±0.26LSB, respectively. SFDR at 5GHz clock frequency for a 273MHz output signal is about 21dB and the power dissipation is less than 37mW.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 513-517)

Pages:

4585-4588

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.513-517.4585

Citation:

Cite this paper

Online since:

February 2014

Authors:

Wen Yuan Li*, Yi Jun Song

Keywords:

CMOS, High-Speed DAC, Pseudo-Thermometer Segmentation

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] Wu X., Palmeras P., Steyaert, M.S. J: A 130nm CMOS 6-bit full Nyquist 3GS/s DAC [J], IEEE J. Solid-State Circuits, 2008(43): 2396-2403.

DOI: 10.1109/asscc.2007.4425702

Google Scholar

[2] Bosch, A.V.D., Borreamans, M.A.F., Steyaert, M.S.J., Sansen, W.: A 10-bit 1-Gsample/s Nyquist current-steering CMOS D/A converter[J], IEEE J. Solid-State Circuits, 2001(36): 315-324.

DOI: 10.1109/4.910469

Google Scholar

[3] R. -L. Chen, H. -W. Ting, S. -J. Chang. Six-bit 2. 7-GS/s 5. 4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers[J]. IEEE J. IET Circuits Devices & Systems, 2011(6): 95-102.

DOI: 10.1049/iet-cds.2011.0192

Google Scholar

[4] S. Luschas and H. -S. Lee. Output impedance requirements for DACs[C]. ISCAS2003, 1, I-861–I-864.

Google Scholar

[5] Jurgen Deveugele, Michhiel S.J. Steyaert. A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC. Solid-State Circuits [J]. 2006(41): 320-329.

DOI: 10.1109/jssc.2005.862342

Google Scholar