Effects of Roughness Scattering in Carrier Transport of Near Ballistic Silicon NanoWire MOSFET

Abstract:

– In this paper, we have investigated the Scattering effects in Carrier Transport of Near-ballistic SiNW MOSFET, which incorporates elastic scattering, optical phonon emission and its combination with Roughness Scattering. Current–voltage (I–V) characteristics of Proposed model is compared with Natori’s Ballistic and Quasi-Ballistic Transport model. We study the impact of Surface Roughness in the device leads on the current variability of a Gate-All-Around (GAA) SiNW MOSFET, which shows a remarkable decrease in electric current, mobility variation and transconductance because of scattered mobility. Analog parameters like the transconductance (g_m), the transconductance generation factor (g_m/I_d), the early voltage (V_A) have also been investigated. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

• Periodical: Applied Mechanics and Materials (Volume 573)
• Pages: 201-208
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.573.201
• Online since: June 2014
• Authors: I.Sheik Arafat*, N.B. Balamurugan, C. Priya
• Keywords: Elastic Scattering, Optical Phonon Emission, Silicon NanoWire (SiNW) MOSFET, Surface Roughness (SR), TCAD

References

[1] K. Natori, Compact modeling of Quasi-ballistic nanowire MOSFETs, IEEE Trans. Electron Devices, vol. 59, no. 1, p.79–86, Jan. (2012).

DOI: 10.1109/ted.2011.2172612

[2] K. Natori, Compact modeling of ballistic nanowire MOSFETs, IEEE Trans. Electron Devices, vol. 55, no. 11, p.2877–2885, Nov. (2008).

DOI: 10.1109/ted.2008.2008009

[3] Yann-Michel Niquet, Hector Mera, and Christophe Delerue, Impurity-limited mobility and variability in gate-all-around silicon nanowires, Applied Physics Letters 100, 153119 (2012).

DOI: 10.1063/1.4704174

[4] S. D. Suk, S. -Y. Lee, S. -M. Kim, E. -J. Yoon, M. -S. Kim, M. Li, C.W. Oh, K. H. Yeo, S. H. Kim, D. -S. Shin, K. -H. Lee, H. S. Park, J. N. Han, C. J. Park, J. -B. Park, D. -W. Kim, D. Park, and B. -I. Ryu, Highperformance 5-nm radius twin silicon nanowire MOSFET (TSNWFET): Fabrication on Bulk Si wafer, characteristics, and reliability, in IEDM Tech. Dig., 2005, p.717.

DOI: 10.1109/iedm.2005.1609453

[5] N. Seoane, A. Martinez, A. R. Brown, J.R. Barker, and A. Asenov, Variability in Si Nanowire MOSFETs due to combined effect of Interface Roughness and random dopants: A fully 3-D NEGF simulation study, IEEE Trans. Electron Devices, vol. 57, no. 7, p.1626–1634, Jul. (2010).

DOI: 10.1109/ted.2010.2048405

[6] R. Barker, Theory of quantum transport in lateral nanostructures, in Physics and Fabrication of Nanostructures, M. Read and W. P. Kirk, Eds. New York: Academic, 1989, p.253–262.

[7] J. R. Barker, M. Finch, J. Pepin, and M. Laughton, Theory of nonlinear transport in quantum waveguides, Solid State Electron., vol. 32, no. 12 p.1155–1159, Dec. (1989).

DOI: 10.1016/0038-1101(89)90206-2

[8] R. Venugopal, Z. Ren, S. Datta, and M. Lundstrom, Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches, J. Appl. Phys., vol. 92, no. 7, p.3730–3739, Oct. (2002).

DOI: 10.1063/1.1503165

[9] A. Martinez, N. Seoane, A. Brown, and A. Asenov, A comparison between a fully 3D real-space versus coupled mode-space NEGF in the study of variability in gate-all-around Si nanowire MOSFET, in Proc SISPAD, San Jose, CA, 2009, p.194–197.

DOI: 10.1109/sispad.2009.5290218

[10] M. Zilli, D. Esseni, P. Palestri, and L. Selmi, On the apparent mobility in nanometric n-MOSFET, IEEE Electron Device Lett., vol. 28, no. 11, p.1036–1039, Nov. (2007).

DOI: 10.1109/led.2007.907553

[11] M. G. Pala, C. Buran, S. Poli, and M. Mouis, Full quantum treatment of surface roughness effects in silicon nanowires and double gate, J. Comput. Electron., vol. 8, no. 3/4, p.374–381, Oct. (2009).

DOI: 10.1007/s10825-009-0289-8

[12] Pai-Chun Chang and Jia Grace Lu, ZnO Nanowire Field-Effect Transistors, IEEE transactions on electron devices, vol. 55, no. 11, november (2008).

DOI: 10.1109/ted.2008.2005181

[13] M. V. Fischetti and S. E. Laux, Monte Carlo studyof electron transportin silicon inversion layers, Phys. Rev. B, vol. 48, no. 4, p.2244–2274, Jul. (1993).

DOI: 10.1103/physrevb.48.2244

[14] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge, UK: Cambridge University Press, (1998).

[15] J. Wang, E. Polizzi and M. Lundstrom, A computational study of ballistic silicon nanowire transistors, IEEE International Electron Dev. Meeting (IEDM), Tech. Digest, pp.695-698, Dec. 8-10 (2003).

DOI: 10.1109/iedm.2003.1269375

[16] H. Majima, Y. Saito and T. Hiramoto, Impact of quantum mechanical effects on design of nano-scale narrow channel n- and p-type MOSFETs, IEEE International+ Electron Dev. Meeting (IEDM) Tech. Digest, pp.951-954, Dec. 3-5 (2001).

DOI: 10.1109/iedm.2001.979618

[17] S. Jin, T. -W. Tang, and M. V. Fischetti, Simulation of silicon nanowire transistors using Boltzmann transport equation under relaxation time approximation, IEEE Trans. Electron Devices, vol. 55, no. 3, p.727–736, Mar. (2008).

DOI: 10.1109/ted.2007.913560