Fault Tolerant Techniques for Finite Field Multipliers

Abstract:

The use of finite field multipliers in the critical applications like elliptic curve cryptography needs Concurrent Error Detection (CED) and correction at architectural level to provide high reliability. This paper discusses fault tolerant technique for polynomial representation based finite field multipliers. The detection and correction are done on-line. We use a combination of Double Modular Redundancy (DMR) and Concurrent Error Detection (CED) techniques. The fault tolerant finite field multiplier is coded in VHDL and simulated using Modelsim. Further, the proposed multiplier with fault tolerant capability is synthesized and results are analyzed with respect to area occupied, input and output pin counts and delay. Our technique, when compared with existing techniques, gives better performance. We show that our concurrent error detecting multiplier over GF(2^m) requires less than 200% extra hardware, whereas with the traditional fault tolerant techniques, such as Triple Modular Redundancy (TMR), overhead is more than 200%.

• Periodical: Applied Mechanics and Materials (Volume 573)
• Pages: 209-214
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.573.209
• Online since: June 2014
• Authors: B. Sargunam*, R. Dhanasekaran
• Keywords: Concurrent Error Detection, Double Modular Redundancy, Finite Field, Triple Modular Redundancy

References

[1] P. K. Meher, On Efficient Implementation of Accumulation in Finite Field Over GF(2m) and its Applications, IEEE Trans. VLSI Systems, Vol. 17, no. 4, pp.541-550, April (2009).

DOI: 10.1109/tvlsi.2008.2005288

[2] A. Reyhani-Masoleh and M. A. Hasan, Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2m), IEEE Trans. Computers, Vol. 53, no. 8, pp.945-959, August (2004).

DOI: 10.1109/tc.2004.47

[3] L. Batina, N. Mentens, S. B. Örs, B. Preneel, Serial Multiplier Architectures over GF(2n) for Elliptic Curve Cryptosystems, in Proc. 12thElectro technical Conf. Melecon 2004., pp.779-782, May (2004).

DOI: 10.1109/melcon.2004.1347047

[4] P. K. Meher, High-Throughput Hardware-Efficient Digit-Serial Architecture for Field Multiplication over GF(2m), in Proc. 6th Int. IEEE-ICICS Conf., December (2007).

DOI: 10.1109/icics.2007.4449560

[5] Zadeh A. A., A Novel Approach for Multiplication over GF(2m) in Polynomial Basis Representation, in Proc. 3rd Int. IEEE-ARES Conf., pp.1346-1351, March (2008).

DOI: 10.1109/ares.2008.208

[6] A. Hariri and A. Reyhani-Masoleh, Concurrent Error Detection in Montgomery Multiplication over Binary Extension Fields, IEEE Trans. Computers, Vol. 60, no. 9, pp.1341-1353, September (2011).

DOI: 10.1109/tc.2010.258

[7] M. Lubaszewski and B. Courtois, A Reliable Fail-Safe System, IEEE Trans. Computers, Vol. 47, no. 2, pp.236-241, Feb (1998).

DOI: 10.1109/12.663771

[8] J. Mathew, A. Costas, A. M. Jabir, H. Rahaman, and D. Pradhan, Single error correcting finite field multipliers over GF(2m), In Proc. Int . Conference on VLSID (VLSID), pp.33-38, January (2008).

DOI: 10.1109/vlsi.2008.105

[9] Jimson Mathew, Abusaleh M. Jabir, and Dhiraj K. Pradhan, Design Techniques for Bit-Parallel Galois Field Multipliers with On-line Single Error Correction and Double Error detection, In Proc. 14th IEEE Int. On-Line Testing Symposium, pp.16-21, (2008).

DOI: 10.1109/iolts.2008.34

[10] W. Chelton M. Benaissa, Concurrent error detection in GF(2m) multiplication and its application in elliptic curve cryptography, IET Circuits Devices Syst, Vol. 2, No. 3, p.289–297, (2008).

DOI: 10.1049/iet-cds:20070184

[11] Siavash Bayat-Sarmadi, and M. Anwar Hasan, Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures, IEEE Transactions on Computers, Vol. 58, no. 11, pp.1553-1567, November (2009).

DOI: 10.1109/tc.2009.62

[12] Chiou-Yng Lee, Concurrent Error Detection in Digit-Serial Normal Basis Multiplication over GF(2m), 22nd Int. Conference on Advanced Information Networking and Applications – Workshops, pp.1499-1504, (2008).

DOI: 10.1109/waina.2008.40

[13] Che Wun Chiou, Chin-Cheng Chang, Chiou-Yng Lee, Ting-Wei Hou, and Jim-Min Lin, Concurrent Error Detection and Correction in Gaussian Normal Basis Multiplier over GF(2m), IEEE Transactions on Computers, Vol. 58, no. 6, pp.851-857, June (2009).

DOI: 10.1109/tc.2008.226

[14] Chiou-Yng Lee, Yu-Hsin Chiu, Jung-Hui Chiu, Concurrent error detection in shifted dual basis multiplier over GF(2m) using cyclic code Approach, 24th Int. Conference on Advanced Information Networking and Applications – Workshops, pp.234-239, (2010).

DOI: 10.1109/waina.2010.113

[15] F. Lima, R. Reis, G. Neuberger, L. Carro, Designing and Testing Fault-Tolerant Techniques for SRAM-Based FPGAs, IEEE Trans. Design and Test of Computers, Vol. 21, no. 6, pp.419-432, December (2004).

DOI: 10.1109/mdt.2004.85