The Viterbi Decoding Scheme for FPGA

Abstract:

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This paper analyzes the principle of Viterbi algorithm which can be used in the norm of the mobile communication system. Then a new Viterbi decoding scheme of (2, 1, 7) convolutional code is presented for FPGA implementation. To take advantage of the FPGA, a new branch weight algorithm and uniform state weight memories is used. At last, a new decoding circuit which can work on 35MHz and can achieve 120 kbs in decoding speed was designed. To use the design of survival path exchange register module, it can decrease the power consumption and the RAM size.

Info:

Periodical:

Edited by:

Helen Zhang and David Jin

Pages:

835-840

DOI:

10.4028/www.scientific.net/AMM.63-64.835

Citation:

K. Han et al., "The Viterbi Decoding Scheme for FPGA", Applied Mechanics and Materials, Vols. 63-64, pp. 835-840, 2011

Online since:

June 2011

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Price:

$35.00

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