The Viterbi Decoding Scheme for FPGA

Ke Han; Zhong Liang Deng; Lian Ming Xu

doi:10.4028/www.scientific.net/AMM.63-64.835

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 63-64The Viterbi Decoding Scheme for FPGA

The Viterbi Decoding Scheme for FPGA

Abstract:

This paper analyzes the principle of Viterbi algorithm which can be used in the norm of the mobile communication system. Then a new Viterbi decoding scheme of (2, 1, 7) convolutional code is presented for FPGA implementation. To take advantage of the FPGA, a new branch weight algorithm and uniform state weight memories is used. At last, a new decoding circuit which can work on 35MHz and can achieve 120 kbs in decoding speed was designed. To use the design of survival path exchange register module, it can decrease the power consumption and the RAM size.

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Periodical:

Applied Mechanics and Materials (Volumes 63-64)

Pages:

835-840

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.63-64.835

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Online since:

June 2011

Authors:

Ke Han, Zhong Liang Deng, Lian Ming Xu

Keywords:

Branch Weight Algorithm, Convolutional Code, Field-Programmable Gate Array (FPGA), Re, Tb, Uniform State Weight Memories, Viterbi Decoding

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References

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