Transistor Resizing Based Low Power Thermal Aware Adder Design on FPGA

Abstract:

In this work, we are going to search the most thermal and energy efficient technology among 90nm, 65nm, 45nm, 40nm and 38nm technology based FPGA, and also searching the most thermal and energy efficient airflow, and heat sink profile. We are also doing thermal analysis for 273.15K-343.15K temperature. we are getting 31.67%, 75.71%, reduction in leakage power for 250LFM and 58.53%, 75.71% reduction in leakage power for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. There is 84.54%, 85.65%, reduction in junction temperature for 250LFM, 84.90%, 85.65%, reduction in junction temperature for 500LFM when we scale down ambient temperature from 343.15K to 283.15K for 65nm, 28nm technology based FPGA. In this work, we are using 90nm Spartan-3E FPGA, 65nm Virtex-5 FPGA, 45nm Spartan-6 FPGA, 40nm Virtex-6 FPGA, and 28nm Artix-7 FPGA. We are taking two different airflow of 250LFM and 500LFM. LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

• Periodical: Advanced Materials Research (Volume 1098)
• Pages: 37-43
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.1098.37
• Online since: April 2015
• Authors: Kartik Kalia*, Khyati Nanda, Arushi Aggarwal, Akshita Goel, Shivani Malhotra
• Keywords: Ambient Temperature, FPGA, Low Power VLSI Design, Thermal Aware, Transistor Resizing

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