I2C and HSTL IO Standard Based Low Power Thermal Aware Adder Design on 45nm FPGA

Abstract:

In this work, we are we are going to search the most thermal and energy efficient IO Standards among the HSTL family and I2C family on 45 nm technology based FPGA. Here we are also doing thermal analysis for 273.15K-343.15K temperature, while during comparing the different IO Standards, we are taking the improvement level at 283.15K. In leakage power analysis, we are getting 9.09% improvement in HSTL with respect to others and in IO power analysis I2C shows 57.89% improvement with respect to others. In thermal analysis for maximum ambient temperature, we observe 1.79% improvement in HSTL_II as compared to others and in Junction Temperature analysis HSTL_I and I2C are 3.6% efficient than others. HSTL_I has minimum Theta Junction to Ambient Temperature value. In this work, we are using 45nm Spartan-6 FPGA. . We are taking airflow of 250LFM where LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

• Periodical: Advanced Materials Research (Volume 1098)
• Pages: 31-36
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.1098.31
• Online since: April 2015
• Authors: Kartik Kalia, Khyati Nanda, Arushi Aggarwal, Akshita Goel, Shivani Malhotra
• Keywords: Ambient Temperature, FPGA, IO Standards, Low Power VLSI Design, Thermal Aware

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