Impact of Different Mobility Models on 32nm Node UTBB SOI MOSFETs

Abstract:

In this work, we investigate by numerical simulation the impact of using standard mobility models versus an inclusion of thin-layer mobility models on 7 nm thin body and 10 nm thin buried oxide (UTBB) SOI MOSFETs of 25 nm gate length (L_g=25 nm). Simulations were performed for both no-ground plane (no-GP) and ground plane (GP) structures for V_ds = 20 mV and 1.0 V and substrate biasing of V_sub = 0 V and 0.5 V. Results of on-current (I_on), off-current (I_off) and linear subthreshold swing (SS_lin) only showed marginal differences between the two mobility models used. Significant differences can only be seen in the values of Drain-Induced Barrier Lowering (DIBL) where in this work is extracted as DIBL=(V_thlin - V_thsat)/ΔV_d. Moreover, the inclusion of thin layer mobility model gives higher values of transconductance (g_m) as compared to standard mobility model.

• Periodical: Advanced Materials Research (Volume 1109)
• Pages: 88-93
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.1109.88
• Online since: June 2015
• Authors: Noraini Othman*, Mohd Khairuddin Md Arshad, Syarifah Norfaezah Sabki, U. Hashim
• Keywords: DIBL, Sentaurus Device Simulator, Thin-Layer Mobility Model, UTBB SOI MOSFETs

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