Power Dissipation Analysis of Adiabatic Circuits and Active Leakage Power Estimation in Nanometer CMOS Processes
The leakage dissipations of nano-circuits have become a critical concern. Estimating the leakage power of nano-circuits is very important in low-power design. This paper presents a new estimation technology for the active leakage dissipations of adiabatic logic circuits. Based on the power dissipation models of adiabatic circuits, active leakage dissipations are estimated by testing total leakage dissipations with additional capacitances on load nodes of the adiabatic circuits using HSPICE simulations. Taken as an example, the estimation for dynamic and active leakage power dissipations of CPAL (Complementary Pass-transistor Adiabatic Logic) circuits is demonstrated using the proposed estimation technology. The simulation results show that the proposed estimation technology can accurately estimate the active leakage dissipations of CPAL circuits with an accepted error over a wide range of frequencies.
Donald C. Wunsch II, Honghua Tan, Dehuai Zeng, Qi Luo
W. Q. Zhang et al., "Power Dissipation Analysis of Adiabatic Circuits and Active Leakage Power Estimation in Nanometer CMOS Processes", Advanced Materials Research, Vols. 121-122, pp. 97-102, 2010