A Parallelization Cost Model for FPGA

Abstract:

Using FPGA for general-purpose computing has become an important research direction in high performance computing technology. However, it is not a lossless optimization method. Due to the impact of hardware reconfiguration overhead, data transmission cost, specific characteristics of programs, and other factors, the speedup of general-purpose computing on FPGA has visible difference. On the basis of in-depth analysis of FPGA architecture and development process, the main factors affecting FPGA implementation performance are pointed out, and a parallel cost model for FPGA based on static program analysis is proposed to provide judgment basis for using FPGA in general-purpose computing. The experiment results show that the algorithm estimates accurately FPGA execution performance.

• Periodical: Advanced Materials Research (Volumes 181-182)
• Pages: 623-628
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.181-182.623
• Online since: January 2011
• Authors: Dan Zhang, Rong Cai Zhao, Lin Han, Jin Qu
• Keywords: Cost Model, Field-Programmable Gate Array (FPGA), Parallel

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