Design and Realization of NAND Flash Based on Embedded Linux System

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Abstract:

This paper utilizes ARM 9 series chips such as S3C2440 as the CPU to realize an embedded Linux system. Due to the integration of NAND Flash in S3C2440, it is easy to connect the NAND Flash external devices in the perspective of hardware. After that, the system combines the serial ports which intend to load and debug the driver of NAND Flash, realizing the loading and uninstalling of NAND Flash storage modules. The innovative design and realization is a basic for the implementation of YAFFS file system in the Linux terminals.

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Periodical:

Advanced Materials Research (Volumes 219-220)

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972-975

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Online since:

March 2011

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© 2011 Trans Tech Publications Ltd. All Rights Reserved

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[1] Joshi, R. and G. Holzmann, A mini challenge: Build a verifiable filesystem. Verified Software: Theories, Tools, Experiments, 2008: pp.49-56.

DOI: 10.1007/978-3-540-69149-5_6

Google Scholar

[2] Min, S., E. Nam, and Y. Lee, Evolution of NAND flash memory interface. Advances in Computer Systems Architecture, 2007: pp.75-79.

DOI: 10.1007/978-3-540-74309-5_9

Google Scholar

[3] Lee, H., et al., An efficient buffer management scheme for implementing a B-tree on NAND flash memory. Embedded Software and Systems, 2007: pp.181-192.

DOI: 10.1007/978-3-540-72685-2_18

Google Scholar

[4] Lim, S. and K. Park, An efficient NAND flash file system for flash memory storage. IEEE Transactions on Computers, 2006: pp.906-912.

DOI: 10.1109/tc.2006.96

Google Scholar

[5] Lee, J., G. Park, and S. Kim, A new NAND-type flash memory package with smart buffer system for spatial and temporal localities. Journal of Systems Architecture, 2005. 51(2): pp.111-123.

DOI: 10.1016/j.sysarc.2004.10.002

Google Scholar

[6] Kim, K., Technology for sub-50 nm DRAM and NAND flash manufacturing. IEDM Tech. Dig, 2005. 144: p.323–326.

Google Scholar

[7] Suh, K., et al., A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. Solid-State Circuits, IEEE Journal of, 2002. 30(11): pp.1149-1156.

DOI: 10.1109/4.475701

Google Scholar

[8] Lee, J. and S. Hur, Effects of floating-gate interference on NAND flash memory cell operation. Electron Device Letters, IEEE, 2002. 23(5): pp.264-266.

DOI: 10.1109/55.998871

Google Scholar