Ternary Logic Dynamic CMOS Comparators
In this paper, a new method of ternary logic circuit design is developed. It’s proposed that two types of static ternary CMOS comparators and three types of dynamic CMOS comparators, designed by new method, with low transistor count, high speed and low power consumption. The proposed comparators are the rearrangement and reordering of transistors in the evaluation block of a dynamic cell. These ternary comparators can be used as equality comparators, mutual comparators and zero/one/two detectors, which are widely used in build in self test and memory testing.
X. Y. Jin et al., "Ternary Logic Dynamic CMOS Comparators", Advanced Materials Research, Vols. 317-319, pp. 1177-1182, 2011