An ASIC Design of a High-Speed Clock and Data Recovery Circuit

Abstract:

Clock and Data Recovery (CDR) means that the digital data streams are sent without an accompanying clock signal. A digital CDR circuit is proposed as it does not depend on the special analog process and provide higher immunity to the noise. This design is fabricated using 0.13μm standard process and the circuit can support up to 5 GHz data rate to support the high speed standard. Compared to other CDR design with more advanced technology, our implementation can have similar performance but the manufacturing cost can be reduced.

• Periodical: Advanced Materials Research (Volumes 403-408)
• Pages: 1218-1223
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.403-408.1218
• Online since: November 2011
• Authors: Chi Wai Ng, Kai Hung Yu, Chiu Wing Sham, C.K. Michael Tse
• Keywords: Clock and Data Recovery, Phase Lock Loop, Voltage Control Oscillator

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