A Fast-Locking ADPLL with Time Measurable DCO

Tae Ho Lim; Ki Jin Kim; S. H. Park; K. H. Ahn

doi:10.4028/www.scientific.net/AMR.433-440.6267

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 433-440A Fast-Locking ADPLL with Time Measurable DCO

A Fast-Locking ADPLL with Time Measurable DCO

Abstract:

This paper proposes a new all digital phase-locked loop (ADPLL) which operates from 80MHz to 800MHz with the locking cycle of less than 40 clock cycles. It employs a time measurable digital controlled oscillator (TMDCO), which helps the reduction of locking cycle. The proposed ADPLL adopts the (8+4)-bit TMDCO and is very insensitive to its linearity and monotonicity characteristics. The validity of the approach is clearly proved by both the analytic method and spectre simulations in a 90-nm fabrication technology.

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Periodical:

Advanced Materials Research (Volumes 433-440)

Pages:

6267-6271

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.433-440.6267

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Online since:

January 2012

Authors:

Tae Ho Lim, Ki Jin Kim, S. H. Park, K. H. Ahn

Keywords:

ADPLL, All Digital PLL, DCO, Digital PLL, PLL, TMC, TMDCO

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References

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