The Improvement of Pseudo-Boolean Satisfiability Algorithm for FPGA Routing

Abstract:

A new routing algorithm is proposed for FPGA to improve the increasing transformation cost of pseudo-Boolean Satisfiability algorithm in the routing process, which combined advantages of pseudo-Boolean Satisfiability and geometric routing algorithm. In the routing process, one of geometric routing algorithm-VPR5.0 was chosen firstly for FPGA routing. If not successful, then use pseudo-Boolean Satisfiability algorithm. Technique of static symmetry-breaking is also adding to carry out pretreatment of pseudo-Boolean constraints, detecting and breaking the symmetries in the routing flow. The purpose was to prune search path, and the cost was consequently reduced. Preliminary experiments results show that the hybrid approach can reduce the runtime observably, speed up the solving process, and have no adverse affect on overall program.

• Periodical: Advanced Materials Research (Volumes 490-495)
• Pages: 1511-1515
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.490-495.1511
• Online since: March 2012
• Authors: Yu Lan Tang, Jian Hui Chen
• Keywords: Benchmarking, Field-Programmable Gate Array (FPGA), Routing Algorithm

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