Built-In Self-Test Scheme for All-Digital Phase-Locked Loops

Abstract:

This paper presents a low-cost Built-In Self-Test (BIST) scheme, which is based on the principle of parity check code. The proposed circuit is consisted of a XOR network, a frequency decrease module, a BIST controller and a fault detector module. Different from the previous methods of PLL BIST, digital signals from the divide-by-N are grouped as transmission codes, and parity check codes are produced synchronously by the BIST controller. Then the results of parity checking are imported to the fault detector and final test results are generated. Purely digital design flow is adopted and hybrid faults models are used to evaluate the efficiency of the circuit. Experimental results indicates that the proposed method can provide the highest test coverage and lower area overhead, which are 98.3% and 4.2%, respectively.

• Periodical: Advanced Materials Research (Volumes 546-547)
• Pages: 922-927
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.546-547.922
• Online since: July 2012
• Authors: Zhi Kuang Cai, Kai Huang, Jun Yang, Long Xing Shi
• Keywords: ADPLL, BIST, Fault Coverage, Parity Check Code

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