A Comparison Study of Three of Input Buffer Designed Using 0.35µm CMOS Technology

Abstract:

In memory device that is contained in the digital application, there is a sequence of input buffer.The input buffer’s function is to improve a digital signal and remove noise. The buffer circuit take these input signal with imperfections and convert them in to full digital logic levels by slicing the signals at correct levels which depends upon the switching point voltage. In this paper,using three topologies, that are NMOS, PMOS and Parallel input buffer. It would be present into design, simulation and analysis of all topologies input buffer. The result in this paper to determine the best of the three topologies to used. The delay time used to determine the best of topologies. Mentor graphic is tools which used in this paper to design and simulation. The technology used in this paper is 0.35 µm CMOS Technology. Analysis of comparison all of topologies used in this paper based on six parameters. The result of comparison analysis can be seen in more details in this explanation.

• Periodical: Advanced Materials Research (Volume 646)
• Pages: 184-190
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.646.184
• Online since: January 2013
• Authors: Shinta Kisriani, Eri Prasetyo Wibowo, Busono Soerowirdjo, Hamzah Afandi, Veronica Ernita Kristianti
• Keywords: Delay, Input Buffer, NMOS, PMOs

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