Comparative Study on Off-State Breakdown Characteristics in Nanowire Junctionless and Inversion Mode Multiple Gate MOSFET

Abstract:

A comparative study on off-state breakdown characteristics in nanowire JL and IM multiple gate MOSFETs has been performed for different gate bias voltages and fin widths. In order to understand the drain breakdown mechanism with different transistor structures, the device was simulated using the 3-dimensional ATLAS software. The band-to-band tunneling current and the gate-induced-drain-leakage current trigger the off-state breakdown in JL transistor and IM transistor, respectively. From experiment and simulation, the off-state breakdown voltage is lower in JL transistor than in IM transistor. As the gate is biased more negatively, the off-state breakdown voltages are increased in JL and IM transistors.

• Periodical: Advanced Materials Research (Volume 684)
• Pages: 295-298
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.684.295
• Online since: April 2013
• Authors: Seung Min Lee, Hyun Jun Jang, Jong Tae Park
• Keywords: CMOS, MOSFET, Nanowire

References

[1] J. T. Park, and J. P. Colinge, Multiple gate SOI MOSFETs: Device design guidelines, IEEE Trans. Electron Device 2002; 49(12) ; 2222-2228.

DOI: 10.1109/ted.2002.805634

[2] J.P. Colinge, C.W. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, R. Murphy, Nanowire transistor without junctions, Nature Nanotechnology, Vol. 5, No. 3, pp.225-229, (2010).

DOI: 10.1038/nnano.2010.15

[3] C.W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. Dehdashti, J.P. Colinge, High temperature performance of silicon junctionless MOSFETs, IEEE Trans Electron Dev. Vol. 57, no. 3, pp.620-625, (2010).

DOI: 10.1109/ted.2009.2039093

[4] C.W. Lee, A. Nazarov, N. Dehdashti, R. Yan, P. razavi, R. Yu, R.T. Doria, J.P. Colinge, Low subthreshold slope in junctionless multigate transistors, Applied Physics letters, vol. 96, p.102106, (2010).

DOI: 10.1063/1.3358131

[5] J.T. Park, J. Y. Kim, J.P. Colinge, Negative-bias-temperature instability and hot carrier effects in nanowire junctionless p-channel multigate transistors, Applied Physics letters, vol. 100, p.083504, (2012).

DOI: 10.1063/1.3688245

[6] K. K. Young, and J. A. Burns, Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFETs, IEEE Trans Electron Dev. 35 (1988), pp.426-431.

DOI: 10.1109/16.2475

[7] C.W. Lee, A. Afzalian, R. Yan, N.D. Akhavan, W. Xiong, and J.P. Colinge, Drain breakdown voltage in MuGFETs : influence of physical parameters, IEEE Trans Electron Dev. 55 (2008), pp.3503-3506.

DOI: 10.1109/ted.2008.2006546

[8] S.M. Lee, S.M. Jeong, W.J. Cho, J.T. Park, Drain breakdown voltage: a comparison between junctionless and inversion mode p-channel MOSFETs, Microelectronics reliability, vol. 52, pp.1945-1948, (2012).

DOI: 10.1016/j.microrel.2012.06.018

[9] T.E. Chang, C. Huang, T. Wang, Mechanism of interface trap-induced drain leakage current in off state n-MOSFETs, IEEE Trans Electron Dev. 42, no. 4, pp.738-743, (1995).

DOI: 10.1109/16.372079

[10] A.N. Nazarov, V.S. Lysenko, I Ferain, S. Das, R. Yu, A. Kranti, N. D. Akhavan, P. Razavi, J.P. Colinge, Floating body effects in junctionless MuGFETs, Proceeding of Eurosoi Workhop, pp.93-94, (2012).

DOI: 10.1016/j.sse.2013.02.056