An Energy-Efficient Approach to Hot-Plugging of Embedded Multiprocessors

Abstract:

With the increasing of the number of processors in one chip, the energy consumption became increasingly important in the low power design of embedded system. In time-sharing OS, different application scenarios lead to different workload. A novel policy for energy saving is that some processors can be hot-plugged on while the workload of the system becomes high and some processors can be hot-plugged off while the workload becomes low. This paper proposed an energy-efficient workload prediction approach called PID prediction algorithm (PPA) which aims dynamic processors number changes for energy saving and reduces the frequency of processors switch on/off for saving extra energy costs. The experiments show that energy consumption is reduced by 19% and the frequency of processors switch on/off is reduced by 30%.

• Periodical: Advanced Materials Research (Volumes 756-759)
• Pages: 4229-4234
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.756-759.4229
• Online since: September 2013
• Authors: Jun Xia
• Keywords: CPU Hot-Plug, Low Power, Multiprocessor, PID

References

[1] G.A. Paleologo, L. Benini, A. Bogliolo, and G. De Micheli, Policy optimization for dynamic power management". In Proceedings of the Design Automation Conference (DAC, 98), IEEE/ACM, p.182–187, San Francisco, June 15–19, (1998).

DOI: 10.1145/277044.277094

[2] E. Grochowski, R. Ronen, J. Shen, and H. Wang, Best of both latency and throughput,. In Proceedings of IEEE International Conference on Computer Design (ICCD 2004), p.236–243, San Jose, October 11–13, (2004).

DOI: 10.1109/iccd.2004.1347928

[3] S. Heo, K. Barr and K. Asanovic, Reducing power density through activity migration,. In Proceedings of International Symposium on Low Power, Electronics and Design (ISLPED), p.217–222, Seoul, August 25–27, (2003).

DOI: 10.1109/lpe.2003.1231865

[4] M. Powell, M. Gomaa, and T.N. Vijaykumar, Heat-and-run: leveraging, SMT and CMP to manage power density through the operating system,. In Proceedings of 11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XI), p.260–270, Boston, October 7–13, (2004).

DOI: 10.1145/1024393.1024424

[5] E. Kursun, C.Y. Cher, A. Buyuktosunoglu, and P. Bose, Investigating, the effects of task scheduling on thermal behavior". 3rd Workshop, on Temperature-Aware Computer Systems (TACS, 06), Boston, June 18, (2006).

[6] K. Nowka, G. Carpenter, E. MacDonald, H.C. Ngo, B. Brock, K. Ishii,T. Nguyen, and J. Burns, A 32-bit PowerPC system-on-a-chip with support, for dynamic voltage scaling and dynamic frequency scaling,. IEEE Journal of Solid-State Circuits, vol. 37, no. 11, p.1600–1608, November, (2002).

DOI: 10.1109/jssc.2002.803941

[7] G. Magklis, G. Semeraro, D.H. Albonesi, S.G. Dropsho, S. Dwarkadas, and M.L. Scott, Dynamic frequency and voltage scaling for a multipleclock-, domain microprocessor,. IEEE Micro, vol. 23, no. 6, p.62–68, Nov/Dec (2003).

DOI: 10.1109/mm.2003.1261388

[8] C. Isci, A. Buyuktosunoglu, C. -Y. Cher, P. Bose, and M. Martonosi, Ananalysis of efficient multi-core global power management policies: maximizing, performance for a given power budget". In Proceedings of the 39th Annual International Symposium on Microarchitetcure (MICRO, 06), IEEE, p.347–358, Orlando, December 9–13, (2006).

DOI: 10.1109/micro.2006.8

[9] Weiser, B. Welch, A. Demers, and S. Shenker. Scheduling for reduced CPU energy. InProc. OSDI, pages 13–23, (1994).