Analysis on Local Congestion of Network-on-Chip

Ming Hua Tang

doi:10.4028/www.scientific.net/AMR.760-762.2183

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 760-762Analysis on Local Congestion of Network-on-Chip

Analysis on Local Congestion of Network-on-Chip

Abstract:

In Network-on-Chip (NoC), adaptive routing provides packets multi paths to reach their destinations. Thus, packets can escape the hot-spot nodes. However, as our study indicates that adaptive routing cannot distribute traffic evenly in the network as expected. A local region will be injected more packets than others, which makes congestion takes place in that local region. Local congestion has significant impact on network performance. In this paper, we carry out a detail studying on local congestion in NoC.

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Periodical:

Advanced Materials Research (Volumes 760-762)

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2183-2187

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.760-762.2183

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Online since:

September 2013

Authors:

Ming Hua Tang

Keywords:

Local Congestion, Network-on-Chip (NoC), Routing Algorithm

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References

[1] F. Steenhof, H. Duque, B. Nilsson, K. Goossens and R. P. Llopis, Networks on Chips for High-End Consumer-Electronics TV System Architectures, Design, Automation and Test in Europe, pp.1-6, (2006).

DOI: 10.1109/date.2006.243840

Google Scholar

[2] W. J. Dally and B. Towles, Route Packets, Not Wires: On-Chip Interconnection Networks, Proc. ACM/IEEE Design Automation Conf., pp.684-689, (2001).

DOI: 10.1109/dac.2001.935594

Google Scholar

[3] L. Benini and G. D. Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computer, vol. 35, no. 1, pp.70-78, Jan. (2002).

DOI: 10.1109/2.976921

Google Scholar

[4] G. -M. Chiu, The Odd-Even Turn Model for Adaptive Routing, IEEE Trans. Parallel and Distributed Systems, vol. 11, no. 7, pp.729-738, July (2000).

DOI: 10.1109/71.877831

Google Scholar

[5] M. Palesi, R. Holsmark, S. Kumar and V. Catania, Application Specific Routing Algorithms for Networks on Chip, IEEE Trans. Parallel and Distributed Systems, vol. 20, pp.316-330, (2009).

DOI: 10.1109/tpds.2008.106

Google Scholar

[6] M. H. Tang and X. L. Lin, Network-on-Chip Routing Algorithms by Breaking Cycles, ICA3PP 2010, pp.163-173, (2010).

Google Scholar

[7] C. J. Glass and L. M. Ni, The Turn Model for Adaptive Routing, J. Assoc. for Computing Machinery, vol. 41, pp.874-902, (1994).

Google Scholar

[8] Sourceforge. net, Noxim: Network-on-chip simulator, 2008. [Online]. Available: http: /noxim. sourceforge. net.

Google Scholar