TDC Implementation Based on Internal Delay Module of FPGA

Rou Gang Zhou; Yun Fei Zhou; Guang Dou Liu; Xiao Tu

doi:10.4028/www.scientific.net/AMR.816-817.1063

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 816-817TDC Implementation Based on Internal Delay Module...

TDC Implementation Based on Internal Delay Module of FPGA

Abstract:

Currently the time to digital converter (TDC) integrated in FPGA performs time-to-digital conversion in the carry chain mode and inter-slot offset is caused to be severe by internal wiring in the FPGA. Based on the carry chain interpolation method, this paper proposes the method for using a delay module in FPGA to achieve accurate signal delay. By calculating the phase difference of multi-clock signal between two latch sampling points, the interval between two sampling points was obtained. Experimental results indicate a measurement accuracy of 78ps or 52ps can be reached by precisely collecting time through the delay module in FPGA. Compared to the carry chain interpolation method, this method is significantly advantageous in small inter-slot offset, stable performance and convenient design and can meet the requirement for time measurement or requirement by laser interferometer with a nm-level accuracy in nuclear physics.

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Periodical:

Advanced Materials Research (Volumes 816-817)

Pages:

1063-1068

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.816-817.1063

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Online since:

September 2013

Authors:

Rou Gang Zhou, Yun Fei Zhou, Guang Dou Liu, Xiao Tu

Keywords:

Field-Programmable Gate Array (FPGA), PS Resolution, Signal Delay, Time-to-Digital Conversion

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