Drain Current Model for Hetero-Dielectric Based TFET Architectures: Accumulation to Inversion Mode Analysis

Abstract:

The paper presents an in-depth study of device physics and development of a generalized model (Accumulation-Depletion-Inversion Mode) for Hetero-Dielectric based TFET Architecture. A comparative study among single dielectric (high-k and low-k dielectric materials) and dual-dielectric (Hetero-Dielectric) based p-i-n and p-n-i-n TFET architectures has also been made. The model includes the impact of dielectric length variation and mobile charge carriers which has been validated through the V_gs and V_ds dependent effective potential at the channel center of the device. Several physics based parameters such as surface potential, energy band profile, total electric field and drain current (both I_ds-V_ds and I_ds-V_ds) have also been investigated. Further, the model has been extended to optimize the Hetero-Dielectric p-n-i-n TFET by tuning the gate work function and length of the dielectric material. While optimization various static parameters such as Subthreshold Swing (SS), threshold voltage, I_on/I_off ratio and dynamic performance parameters (parasitic capacitances) i.e. total gate capacitance (C_gg), gate to source capacitance (C_gs) and gate to drain capacitance (C_gd) have been investigated. The efficacy of the model has been validated through simulation results obtained using ATLAS device simulator.

• Periodical: Journal of Nano Research (Volume 36)
• Pages: 31-43
• DOI: https://doi.org/10.4028/www.scientific.net/JNanoR.36.31
• Online since: November 2015
• Authors: Upasana Upasana, Rakhi Narang, Manoj Saxena, Mridula Gupta*
• Keywords: Accumulation Mode, Depletion Mode, Hetero-Dielectric TFET, Inversion Mode, Optimization, p-i-n TFET, p-n-i-n TFET

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