Modeling and Simulation of Nanoscale Lateral Gaussian Doped Channel Asymmetric Double Gate MOSFET

Article Preview

Abstract:

This work presents the drain current model using Evanescent Mode Analysis (EMA) for nanoscale Double Gate MOSFET having Gaussian doping profile along the horizontal direction in the channel i.e. from source to drain region. Due to heavily doped channel, band gap narrowing effect is incorporated in the analytical modeling scheme. The various parameters evaluated in this work using analytical modeling scheme are surface potential, electric field, threshold voltage, sub-threshold slope and drain current. The impact of peak Gaussian doping profile on the drain current and trans-conductance has been demonstrated which are important for assessing the analog performance of the device. The results are also compared with the uniformly doped DG MOSFET. The asymmetric behaviour of Gaussian doped DG MOSFET has also been investigated. In addition to this, digital performance of Gaussian doped DG MOSFET has also been assessed using exhaustive device simulation.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

51-63

Citation:

Online since:

November 2015

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2016 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

* - Corresponding Author

[1] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance, IEEE Electron Device Letters, 8, (1987) 410-412.

DOI: 10.1109/edl.1987.26677

Google Scholar

[2] L. Huaxin and Y. Taur, An analytic potential model for symmetric and asymmetric DG MOSFETs, IEEE Trans. on Electron Device, 53 (2006) 1161-1168, (2006).

DOI: 10.1109/ted.2006.872093

Google Scholar

[3] F. Djeffal, T. Bentrcia, M.A. Abdi, T. Bendib, Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects, Microelectronics Reliability, 51 (2011) 550-555.

DOI: 10.1016/j.microrel.2010.10.002

Google Scholar

[4] V. Kumari, M. Saxena, R. S. Gupta, and M. Gupta, Two dimensional Analytical Drain Current Model for Double Gate MOSFET Incorporating Dielectric Pocket, IEEE Trans. Electron Devices, 59 (2012) 2567-2574.

DOI: 10.1109/ted.2012.2206030

Google Scholar

[5] A. Dey, A. Chakravorty, V. Das Gupta and A. Das Gupta; Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs, IEEE Trans. on Electron Devices, 55 (2008) 3442-3449.

DOI: 10.1109/ted.2008.2006109

Google Scholar

[6] P. K. Tiwari and S. Jit, A Subthreshold Swing Model for Symmetric Double Gate (DG) MOSFETs with Vertical Gaussian Doping, Journal of Semiconductor Technology and Science, 10 (2010) 107-117.

DOI: 10.5573/jsts.2010.10.2.107

Google Scholar

[7] S. Dubey, P. K. Tiwari, and S. Jit, On-current modeling of short-channel double-gate (DG) MOSFETs with a vertical Gaussian like doping profile, Journal of semiconductor, 34 (2013) 054001 (8).

DOI: 10.1088/1674-4926/34/5/054001

Google Scholar

[8] G. Zhang Z. Shao and K Zhou, Threshold voltage model for short channel FD-SOI MOSFETs with vertical Gaussian profile, IEEE Trans. Electron Devices, 55 (2008) 803-809.

DOI: 10.1109/ted.2007.914832

Google Scholar

[9] A. Nandi, A. K. Saxena, and S. Das Gupta, Analytical Modeling of a Double Gate MOSFET Considering Source/Drain Lateral Gaussian Doping Profile, IEEE Transaction On Electron Devices, 60 (2013) 3705 – 3709.

DOI: 10.1109/ted.2013.2282632

Google Scholar

[10] ATLAS: 3-D Device Simulator, SILVACO International, Version 5. 14. 0. R, (2010).

Google Scholar

[11] J. Lee, and H. Shin, Evanescent-Mode Analysis of Short-Channel Effects in MOSFETs, J. of Korean Physical Society, 44 (2004) 50-55.

Google Scholar

[12] D. J. Frank, Y. Tuar, and H. S. P. Wong, Generalized scale length for two dimensional effects in MOSFETs, IEEE Electron Devices Lett., 19 (1998) 385-387.

DOI: 10.1109/55.720194

Google Scholar

[13] J.W. Slotboom and H. C. Graff, Measurements of bandgap narrowing in Si bipolar transistors, J. Solid State Electron., 19 (1976) 857–862.

DOI: 10.1016/0038-1101(76)90043-5

Google Scholar

[14] J. B. Roldan, F. Gamiz, J .A. Lopez-Villanueva, and J. E. Carceller, Modeling effects of electron velocity overshoot in a MOSFET, IEEE Trans. Electron Devices, 44 (1997) 841-846.

DOI: 10.1109/16.568047

Google Scholar

[15] A. Tsormpatzoglou, C. A. Dimitriadis, M. Mouis, G. Ghibaudo and N. Collaert, Experimental characterization of the sub-threshold leakage current in triple-gate FinFETs, Solid State Electron., 53 (2009) 359-363.

DOI: 10.1016/j.sse.2009.01.008

Google Scholar

[16] D. Jiménez, B. Iñíguez, J. Suñé and J. J. Sáenz, Analog performance of the nanoscale double-gate metal-oxide-semiconductor field-effect-transistor near the ultimate scaling limits, J. of Applied Physics, 96 (2004)5271-5276.

DOI: 10.1063/1.1778485

Google Scholar

[17] N. H. E. Weste, D. Harris, and A. Banerjee, CMOS VLSI design: A circuit and system perspective, Dorling Kindersley (India) Pvt. Ltd. (2006).

Google Scholar