Analytical Drain Current Model for Fully Depleted Surrounding Gate TFET

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In this paper, we propose the analytical modeling for fully depleted surrounding gate TFET surrounding gate tunneling field effect transistor with single metal gate. This model comprises the surface potential using 2-D Poisson’s equation and drain current with the effects of oxide thickness, silicon thickness as radius, drain voltage, gate metal work function, and assuming channel is fully depleted. The model is tested using TCAD Simulation Tool.

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75-81

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C. Usha and P. Vimala, "Analytical Drain Current Model for Fully Depleted Surrounding Gate TFET", Journal of Nano Research, Vol. 55, pp. 75-81, 2018

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November 2018

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