Analytical Drain Current Model for Fully Depleted Surrounding Gate TFET

Abstract:

In this paper, we propose the analytical modeling for fully depleted surrounding gate TFET surrounding gate tunneling field effect transistor with single metal gate. This model comprises the surface potential using 2-D Poisson’s equation and drain current with the effects of oxide thickness, silicon thickness as radius, drain voltage, gate metal work function, and assuming channel is fully depleted. The model is tested using TCAD Simulation Tool.

• Periodical: Journal of Nano Research (Volume 55)
• Pages: 75-81
• DOI: https://doi.org/10.4028/www.scientific.net/JNanoR.55.75
• Online since: November 2018
• Authors: C. Usha*, P. Vimala
• Keywords: Drian Current, Surface Potential, Surrounding Gate, Threshold Voltage, Tunneling Field Transistor (TFET)

References

[1] E. P. Vanndamme, P. Janson, and L. Deferen, Modelling the subthresholdswing in MOSFETS, IEEE Electron Device Letters. vol. 18, no.8, pp .369-371, Aug. (1997).

[2] Young KK. Short-channel effect in fully-depleted SOI MOSFETs. IEEE T Electron Dev 1989; 36: 399-402.

DOI: 10.1109/16.19942

[3] Skotnicki T, Merckel G, Pedron T. The voltage-doping transformation and new approach to the modeling of MOSFETs short-channel effects. IEEE Electr Device L 1988; 9: 109-112.

DOI: 10.1109/55.2058

[4] Vimala, P.; and Balamurugan, N.B. (2013). Modelling and simulation of centroid and inversion charge density in cylindrical surrounding gateMOSFETs including quantum effects.Journal of Semiconductors,34(11), 1-6.

DOI: 10.1088/1674-4926/34/11/114001

[5] C.Usha and Dr.P.Vimala,A Tunneling FET exploiting in various Structure and Different Models: Review in IEEE ICIIECS'15 at Karpagam College of Engineering, Coimbatore, Tamilnadu, India.

DOI: 10.1109/iciiecs.2015.7192878

[6] Colinge JP. Multiple-gate SOI MOSFETs. Solid State Electron 2004; 48: 897-905.

DOI: 10.1016/j.sse.2003.12.020

[7] Park JT, Colinge JP. Multiple-gate SOI MOSFETs: device design guidelines. IEEE T Electron Dev 2002; 49.

DOI: 10.1109/ted.2002.805634

[8] Kranti A, Haldar S, Gupta RS. Analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET. Microelectron Eng 2001; 56: 241-259.

DOI: 10.1016/s0167-9317(00)00419-6

[9] Seabaugh AC, Zhang Q. Low-voltage tunnel transistors for beyond CMOS logic. P IEEE 2010; 98: 2095-2110.

DOI: 10.1109/jproc.2010.2070470

[10] Ionescu AM, Riel H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 2011; 479: 329-337.

DOI: 10.1038/nature10679

[11] Lu H, Seabaugh A. Tunnel field-effect transistors: state-of-the-art. IEEE J Electron Devices Soc 2014; 2: 44-49.nnel field-effect transistor", J.Appl.Phys.,vol.107,np. 2, pp.024518-6, Jan. (2010).

DOI: 10.1109/jeds.2014.2326622

[12] A. S. Verhulst, B.Soree, D.Leonelli, W.G. Vandenberghe, and G.Groeseneken, Modelling the single-gate, double-gate, and gate-all-around tunnel field effect transistors,, J. Appl. Phys., vol. 107, no. 2, pp.024518-1–024518-6, (2010).

DOI: 10.1063/1.3277044

[13] Zhang L, Lin X, He J, Chan M. An analytical charge model for double-gate tunnel FETs. IEEE T Electron Dev 2012; 59: 3217-3223.

DOI: 10.1109/ted.2012.2217145

[14] E.O. Kane,Zener tunneling in semiconductors,,J.Phys.Chem.Solids, vol.12,no. 2,pp.181-188, Jan.(1960).

[15] Bhushan B, Nayak K, Rao VR. DC compact model for SOI tunnel field- effect transistors. IEEE T Electron Dev 2012; 59: 2635-2642.

DOI: 10.1109/ted.2012.2209180

[16] Cui N, Liu L, Xie Q, Tan Z, Liang R, Wang J, Xu J. A two-dimensional analytical model for tunnel field effect transistor and its applications. Jpn J Appl Phys 2013; 52: 0443031.

DOI: 10.7567/jjap.52.044303

[17] Wan J, Royer CL, Zaslavsky A, Cristoloveanu S. A tunneling field effect transistor model combining inter-band tunneling with channel transport. J Appl Phys 2011; 110: 10450301.

DOI: 10.1063/1.3658871

[18] Lee MJ, Choi W. Analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs). Solid State Electron 2011; 63: 110-114.

DOI: 10.1016/j.sse.2011.05.008

[19] Bardon MG, Neves HP, Puers R, Van HC. Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions. IEEE T Electron Dev 2010; 57: 827-834.

DOI: 10.1109/ted.2010.2040661

[20] Pan A, Chui CO. A quasi-analytical model for double-gate tunneling field-effect transistors. IEEE Electr Device L 2012; 33: 1468-1470.

DOI: 10.1109/led.2012.2208933

[21] Hraziia, Vladimirescu A, Amara A, Anghel C. An analysis on the ambipolar current in Si double-gate tunnel FETs. Solid State Electron 2012; 70: 67-72.

DOI: 10.1016/j.sse.2011.11.009

[22] Yadav M, Bulusu A, Dasgupta S. Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: potential and electric field. Microelectr J 2013; 44: 1251-1259.

DOI: 10.1016/j.mejo.2013.08.011

[23] Narang R, Saxena M, Gupta RS, Gupta M. Drain current model for a gate all around (GAA) p-n-p-n tunnel FET. Microelectr J 2013; 44: 479-488.

DOI: 10.1016/j.mejo.2013.04.002

[24] Vishnoi R, Kumar MJ. Compact analytical drain current model of gate-all-around nanowire tunneling FET. IEEE T Electron Dev 2014; 61: 2599-2603.

DOI: 10.1109/ted.2014.2322762

[25] Dash S, Mishra GP. A 2-D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance. Advances in Natural Sciences: Nanoscience and Nanotechnology 2015; 6: 035005-1-10.

DOI: 10.1088/2043-6262/6/3/035005

[26] J. Wan, C. L. Royer, A. Zaslavsky, and S. Cristoloveanu, A tunneling field effect transistor model combining interband tunneling with channel transport, J. Appl. Phys., vol. 110, no. 10, pp.104503-1–104503-7, (2011).

DOI: 10.1063/1.3658871

[27] Rajat Vishnoi and M.Jagadesh Kumar, Compact Analytical Drain Current Model of Gate-All- Around Nanowire Tunneling FET, IEEE Transactions on Electron Devices., vol. 61, No. 7, pp.2599-2603, (2014).

DOI: 10.1109/ted.2014.2322762