Preparation of Multilayer Barium Titanate PTC Thermistor with Low Room Temperature Resistance

Dong Xiang Zhou; Huan Liu; Shu Ping Gong; Dao Li Zhang

doi:10.4028/www.scientific.net/KEM.280-283.1921

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HomeKey Engineering MaterialsKey Engineering Materials Vols. 280-283Preparation of Multilayer Barium Titanate PTC...

Preparation of Multilayer Barium Titanate PTC Thermistor with Low Room Temperature Resistance

Abstract:

Chip-type PTC thermistors with multilayer stacked structure have been fabricated by bonding sintered ceramic chips with internal electrodes to offer low resistance at room temperature and correspondence to surface mounted technology. The resistance-temperature characteristics of multiplayer stacked PTC thermistors made up of different numbers (N = 1, 3, 5) of layers were experimentally investigated (the typical size of each layer was 10 mm × 7.0 mm × 0.38 mm). The selection and extraction of additives in roll-forming process were also discussed. This resulted in a crack-free multiplayer stacked PTC thermistor.