Design of a Digital Decimation Filter for High-Precision 4-Order Sigma-Delta ADC

Wei Ping Chen; Qiang Fu; Xiao Wei Liu; Yan Xiao; Bin Zhang; Yu Heng Yang

doi:10.4028/www.scientific.net/KEM.503.415

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HomeKey Engineering MaterialsKey Engineering Materials Vol. 503Design of a Digital Decimation Filter for...

Design of a Digital Decimation Filter for High-Precision 4-Order Sigma-Delta ADC

Abstract:

In this paper, a design of a digital decimation filter which has a output of 24 bits for high-precision 4-ordes Σ-Δ ADC is proposed. The digital decimation filter includes a CIC filter, a compensation filter and a half band filter. The over-sampling rate of the digital decimation filter is 256, the cutoff frequency is 1kHz, the coefficient of the pass-band ripple is -0.25dB, the stop-band attenuation is -162dB, simulation results using Matlab and modelsim are correct, the result of the FPGA verification shows that the design meet the requirement of the high-precision 4-ordes Σ-Δ ADC.

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Periodical:

Key Engineering Materials (Volume 503)

Pages:

415-419

DOI:

https://doi.org/10.4028/www.scientific.net/KEM.503.415

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Online since:

February 2012

Authors:

Wei Ping Chen, Qiang Fu, Xiao Wei Liu, Yan Xiao, Bin Zhang, Yu Heng Yang

Keywords:

CSD, Digital Decimation Filter, Σ-Δ ADC

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References

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