System-Level Simulation and Fabrication of On-Chip Fatigue Bending Test Structure for Micro-Scale Polysilicon Films

Le Guan; Jia Li Gao; Qi Liu; Bin Li; Jin Kui Chu

doi:10.4028/www.scientific.net/KEM.562-565.930

Paper Titles

Structural and Photoluminescence Characteristics of ZnTiO₃:Pb²⁺ Nanofibers Produced by Electrospinning
p.908

Structure and Mechanical Property of Asio Otus Feather Barbs
p.914

Study on the Preparation of Streptomycin Imprinted Polymers on the Surface of Silica Micro and Nano Spheres
p.920

Synthesis of High Density Boron Nitride Nanotube Film
p.926

System-Level Simulation and Fabrication of On-Chip Fatigue Bending Test Structure for Micro-Scale Polysilicon Films
p.930

The Effects of RE and Si on the Thickness and Cross Section Morphology of Zn-6Al-3Mg Alloy Coating
p.935

The Fabrication of Piezoelectric Vibration Energy Harvester Arrays Based on AlN Thin Film
p.942

The Study of Porous Anodic Alumina as Template for the Pit Initiation on Electrode Aluminum Foils
p.947

Influences of Crystallization Temperature and Slurry Concentration on Stress of PZT Thick Film Prepared by a Modified Sol-Gel Method
p.952

HomeKey Engineering MaterialsKey Engineering Materials Vols. 562-565System-Level Simulation and Fabrication of On-Chip...

System-Level Simulation and Fabrication of On-Chip Fatigue Bending Test Structure for Micro-Scale Polysilicon Films

Abstract:

Two kind of on-chip integrated fatigue bending test structures are designed through system-level simulation method based on macromodels to measure the fracture strength and fatigue mechanical properties of polysilicon thin films. The first on-chip fatigue test structure is actuated by V-beam thermal actuator, and the other test structure actuated by electrostatic comb. The static and dynamic analysis was performed by Coventorware Architect module using self-bulid reduced order model described with the MAST hardware language and some other commercial parts from Coventorware parts library. The structural dimension parameters are determined and optimized according to system-level simulation and the computing result has shown that the self-build macromodels and the on-chip integrated test system are efficient and reliable. Two kinds of polysilicon on-chip fatigue bending test structure were fabricated with two-layer polysilicon surface micromachining process in Institute of Microelectronics, Peking University.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Key Engineering Materials (Volumes 562-565)

Pages:

930-934

DOI:

https://doi.org/10.4028/www.scientific.net/KEM.562-565.930

Citation:

Cite this paper

Online since:

July 2013

Authors:

Le Guan, Jia Li Gao, Qi Liu, Bin Li, Jin Kui Chu

Keywords:

Fatigue Bending Test, MEMS, Model Order Reduction

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] H. Kapels, R.Aigner, J.Binder, Fracture strength and fatigue of polysilicon determined by a novel thermal actuator, IEEE. Trans. Electri. Dev. 47 (2000) 1522-1528.

DOI: 10.1109/16.848302

Google Scholar

[2] C. L. Muhlstein, S. B. Brown, R. O. Ritchie, High-cycle fatigue of single-crystal silicon thin films, J. Microelectromechanical Syst.10 (2001) 593-600.

DOI: 10.1109/84.967383

Google Scholar

[3] D. H. Alsem, O. H. Pierron and E. A. Stach et al., Mechanisms for fatigue of micron-scale silicon structural films, Adv. Eng. Mater, 9(2007) 15-30.

DOI: 10.1002/adem.200600269

Google Scholar

[4] A. Corigliano, B. D. Masi and A. Frangi et al., Mechanical characterization of polysilicon through on-chip tensile tests J, Microelectromech. Syst. 13(2004) 200–219.

DOI: 10.1109/jmems.2003.823221

Google Scholar

[5] L. Guan, J. L. Gao and J. K. Chu, Design and system-level simulation of a novel on-chip test based on macromodels, Key. Eng. Mate, 483 (2011) 38-42.

DOI: 10.4028/www.scientific.net/kem.483.38

Google Scholar

[6] Y.Y. Wang, G. Y. Wu, Y. L. Hao et al., Study of silicon-based MEMS technology and its Standard process, Chinese. J. Electro. 30 (2002) 1577-1584. (in Chinese)

Google Scholar

[7] GEMAC Inc.HT133 evaluation circuit for capacitive sensors. (2004).

Google Scholar