A Residue Number System Based Time-to-Digital Converter Architecture and its FPGA Implementation

Cong Bing Li; Haruo Kobayashi

doi:10.4028/www.scientific.net/KEM.698.127

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HomeKey Engineering MaterialsKey Engineering Materials Vol. 698A Residue Number System Based Time-to-Digital...

A Residue Number System Based Time-to-Digital Converter Architecture and its FPGA Implementation

Abstract:

A time-to-digital converter (TDC) based on residue number system is presented. This architecture can reduce hardware and chip area as well as power significantly compared to a flash-type TDC while keeping comparable performance. Its proof-of-concept prototype was implemented on FPGA, and the measurement results validate the effectiveness of the proposed architecture

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Periodical:

Key Engineering Materials (Volume 698)

Pages:

127-132

DOI:

https://doi.org/10.4028/www.scientific.net/KEM.698.127

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Online since:

July 2016

Authors:

Cong Bing Li*, Haruo Kobayashi

Keywords:

FPGA, Residue Number System, Time-To-Digital Converter, Timing Measurement

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