Impact of LPCVD TEOS Thickness on Vt-Pushout in Flash Memory Cell due to Mechanical Stress

Pooi Heong Teoh; Georg Temple; Chin Che Tin

doi:10.4028/www.scientific.net/KEM.701.73

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HomeKey Engineering MaterialsKey Engineering Materials Vol. 701Impact of LPCVD TEOS Thickness on Vt-Pushout in...

Impact of LPCVD TEOS Thickness on Vt-Pushout in Flash Memory Cell due to Mechanical Stress

Abstract:

This paper reports on the dependence of cycling or endurance in flash memory with the stress induced by low-pressure chemical vapor deposition (LPCVD) process. The deposited 12.5nm tetraethyl orthosilicate (TEOS) layer served as sacrificial oxide during source/drain (S/D) implantation, which was then subsequently removed. However, this deposited TEOS layer has been found to induce a stress on the channel which affects the flash memory cycling or endurance performance.

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Key Engineering Materials (Volume 701)

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73-76

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https://doi.org/10.4028/www.scientific.net/KEM.701.73

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July 2016

Authors:

Pooi Heong Teoh, Georg Temple, Chin Che Tin

Keywords:

Cycling, Endurance, LPCVD TEOS, Stress Memorization Technique (SMT)

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References

[1] M.S. Chen, Y.K. Fang, T.H. Lee, C.T. Lin, Y.T. Chiang, J. Ko, Y.K. Sheu, T.L. Shen, and W.Y. Liao, Effect of Etch Stop Layer Stress on Negative Bias Temperature Instability of Deep Submicron p-Type Metal–Oxide–Semiconductor Field Effect Transistors with Dual Gate Oxide, Japanese Journal of Applied Physics 47 (2008).

DOI: 10.1143/jjap.47.2624

Google Scholar

[2] A. Toda, S. Fujieda, K. Kanamori, J. Suzuki, K. Kuroyanagi, N. Kodama, Y. Den, and O. Nishizaka, Impact of Mechanical Stress on Interface Trap Generation in Flash EEPROMs, Proceedings of the 43rd Annual International Reliability Physics Symposium, 2005, pp.250-256.

DOI: 10.1109/relphy.2005.1493093

Google Scholar

[3] S.E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, A 90-nm Logic Technology Featuring Strained-Silicon, IEEE Transactions On Electron Devices 51 (2004).

DOI: 10.1109/ted.2004.836648

Google Scholar

[4] I.S. Han, H.H. Ji, O.S. You, W.H. Choi, J.E. Lim, K.J. Hwang, S.H. Park, H.S. Lee, D.B. Kim, H.D. Lee, New Observation of Mobility and Reliability Dependence on Mechanical Film Stress in Strained Silicon CMOSFETs, IEEE Transactions On Electron Devices 55 (2008).

DOI: 10.1109/ted.2008.921061

Google Scholar