Influence of Cell Design and Gate-to-Source Voltage on Avalanche Robustness of SiC MOSFET Integrated JBS Diode

Chong Yu Jiang; Hong Yi Xu; Song Lin Yang; Heng Yu Wang; Na Ren; Kuang Sheng

doi:10.4028/p-f1aq7k

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HomeKey Engineering MaterialsKey Engineering Materials Vol. 945Influence of Cell Design and Gate-to-Source...

Influence of Cell Design and Gate-to-Source Voltage on Avalanche Robustness of SiC MOSFET Integrated JBS Diode

Abstract:

In this work, 1200 V SiC JMOS devices with different W_sch (2 μm, 2.5 μm and 3 μm) are fabricated. The single unclamped inductive switching (UIS) tests under different V_{gs_off} (-5 V and 0 V) are carried out to investigate the avalanche capability. The avalanche robustness among various W_sch under same V_{gs_off} is also compared and analyzed by simulation. The different failure mechanisms between different V_{gs_off} are studied by failure analysis and simulation. The method of improving avalanche ruggedness of JMOS is proposed.

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Periodical:

Key Engineering Materials (Volume 945)

Pages:

71-76

DOI:

https://doi.org/10.4028/p-f1aq7k

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Cite this paper

Online since:

May 2023

Authors:

Chong Yu Jiang, Hong Yi Xu, Song Lin Yang*, Heng Yu Wang, Na Ren, Kuang Sheng

Keywords:

Avalanche Robustness (UIS Capability), Failure Mechanism, SiC MOSFET Integrated JBS Diode

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Creative Commons CC BY 4.0

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* - Corresponding Author

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