A Scalable SPICE Electrothermal Compact Model for SiC MOSFETs: A Comparative Study between the LEVEL-3 and the BSIM

Alessandro Borghese; Michele Riccio; Luca Maresca; Giovanni Breglio; Andrea Irace

doi:10.4028/p-hmxz8o

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A Scalable SPICE Electrothermal Compact Model for SiC MOSFETs: A Comparative Study between the LEVEL-3 and the BSIM
p.135

HomeKey Engineering MaterialsKey Engineering Materials Vol. 946A Scalable SPICE Electrothermal Compact Model for...

A Scalable SPICE Electrothermal Compact Model for SiC MOSFETs: A Comparative Study between the LEVEL-3 and the BSIM

Abstract:

In this paper, two implementations of a SPICE-based compact model for SiC MOSFETs are presented. The two versions rely on widely adopted LEVEL-3 and BSIM 4.6.1 models, respectively. The paper discusses the feasibility of adopting these two models for the description of SiC power MOSFETs. Furthermore, after calibrating the DC characteristics on target experimental data coming from 1.7 kV-60 A MOSFETs, a comparison between the accuracy of the two is presented.

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Periodical:

Key Engineering Materials (Volume 946)

Pages:

135-140

DOI:

https://doi.org/10.4028/p-hmxz8o

Citation:

Cite this paper

Online since:

May 2023

Authors:

Alessandro Borghese*, Michele Riccio, Luca Maresca, Giovanni Breglio, Andrea Irace

Keywords:

BSIM, Compact Modeling, Electrothermal Simulation, SiC MOSFET, SPICE, TCAD

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Creative Commons CC BY 4.0

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* - Corresponding Author

References

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