Materials Science Forum Vol. 1014

Abstract: A novel silicon carbide (SiC) trenched schottky diode with step-shaped junction barrier is proposed for superior static performance and large design window. In the proposed diode, to improve tradeoff between specific on-resistance and surface peak electric field, the shape of the trenched-junction is modified to stair-step, without extra fabrication process. To investigate the performances of the SiC step-shaped trenched junction barrier schottky (SSTJBS) diode, numerical simulations are carried out through Silvaco TCAD. The results indicate that the proposed diode can accommodate highly doped drift region with no degradation of its reverse blocking characteristic. In comparison with the conventional SiC trenched junction barrier schottky (TJBS) diode, the proposed SiC SSTJBS diode shows a larger design window of drift region doping concentration from 7.9×10¹⁵cm^-3 to 9.5×10¹⁵cm^-3. In the design window, the specific on-resistance and surface peak electric field can be reduced by 12.9% and 11%, respectively.

Abstract: Successes of GaN and SiC electronics in high frequency, large power realm indicate that, the GaN/SiC hetero-structures can be used to design the impact avalanche transit time (IMPATT) diodes operating at Terahertz range, of which holds advantages over homo-structural counterparts in lower noise and reduced tunnel current. Here, the (n)GaN/(p)SiC and (p)GaN/(n)SiC double drift region (DDR) IMPATT diodes operating at 0.85 THz are proposed based on the quantum corrected drift-diffusion (QCDD) model, the performance parameters of static state, large signal and noise properties of the studied devices such as peak electric field intensity, breakdown voltage, optimal negative conductance, output power, conversion efficiency, admittance-frequency relation, quality factor, noise electric field, mean-square noise voltage per band-width and noise measure were numerically calculated and analyzed, which can guide to optimize the GaN/SiC IMPATT diodes.

Abstract: With the development of high-voltage switches and high-speed RF circuits, the enhancement mode(E-mode) AlGaN/GaN HEMTs have become a hot topic in those fields. The E-mode GaN-based HEMTs have channel current at the positive gate voltage, greatly expanding the device in low power digital circuit applications. The main methods to realize E-mode AlGaN/GaN HEMT power devices are p-GaN gate technology, recessed gate structure, fluoride ion implantation technology and Cascode structure (Cascode). In this paper, the advantage and main realizable methods of E-mode AlGaN/GaN HEMT are briefly described. The research status and problems of E-mode AlGaN/GaN HEMT devices fabricated by p-GaN gate technology are summarized. The advances of p-GaN gate technology, and focuses on how these research results can improve the power characteristics and reliability of E-mode AlGaN/GaN HEMT by optimizing device structure and improving process technology, are discussed.

Abstract: In this study, we propose a novel normally-off AlGaN/GaN HFET based on stack AlGaN barrier structure and p-type NiO gate. The residual thin AlGaN barrier (with low Al content) is adopted to alleviate mobility degradation. Besides, p-type conductive NiO formed by thermal oxidation at 500 °C was used as gate electrode, which contribute to the positive shift of threshold voltage. Combining NiO gate and thin barrier structure, normally-off device with a threshold voltage of +1.1 V is realized. Temperature dependent transfer characteristics show that the normally-off device presents good thermally stability within the temperature range from 25 to 150 °C.

Abstract: In this paper, 4H-SiC planar MOSFETs were designed and fabricated. By using TCAD tool, the trade-off between on-resistance and maximum gate oxide electric field was optimized. With optimized gate oxide growth process, the gate oxide’s critical electric field of 9.8 MV/cm and the effective barrier height of 2.57 eV between SiO₂ and 4H-SiC were obtained. The field effective mobility with different p-body doping was compared and studied. The MOS interface state density of 1.12E12 cm^-2eV^-1 at E_C - E_IT = 0.21 eV and channel mobility of 19.3 cm²/Vs at V_GS = 20 V were obtained. The fabricated MOSFET’s on-resistance of 6.4 mΩcm² was obtained with hexagonal cell structure which is very consistent with the simulation results.

Abstract: In this paper, SiC MOS capacitors were fabricated and annealed in Ar/O₂ = 9:1 ambient with different temperature, and the annealing effects on the reliability and performance of SiC MOS capacitance were investigated. We found that annealing in Ar/O₂ ambient is capable to improve the reliability of gate oxide. When annealing in higher temperature, defects near SiO₂/SiC interface are reduced, but the gate reliability deteriorated. It is difficult to obtain the best performance and reliability under the same conditions. There is a trade-off between D_it and reliability to adjust the annealing conditions.

Abstract: In this paper, a High-K dielectric permittivity Enhanced Depletion-JTE(HKED-JTE) for 10 kV ultra-high voltage is studied. The HKED-JTE improves the terminal protection efficiency by the self-charge balance of High-K dielectric polarization charges. The tolerance of the implantation dose window of HKED-JTE reaches 9 times as large as that of normal TZ-JTE with the same terminal area, and the corresponding BV holding theoretical breakdown voltage is over 80%. The thicker High-K layer accomplishes the modulation of the surface electric flux and decreases the electric field up to 51% and 47% at the abrupt junction J2 and J3 along the device interface between the SiC and High-K materials.

Abstract: A 10kV/100A SiC PiN rectifier with MRM-JTE (multiple-ring modulated junction termination extension) is designed, fabricated and characterized. The optimized MRM-JTE achieves high breakdown capability and extends the optimal JTE dose window. A 100μm thick epitaxial SiC PiN rectifier with a doping concentration of 5×10¹⁴cm⁻³ has been fabricated using a standard TZ-JTE process. A 5.4V forward voltage drop is obtained at 100A forward current. Moreover, a measured breakdown voltage is up to 13.5kV corresponding to about 96% of the ideal parallel plane junction. The fabricated device exhibits a low R_ON,SP of 3.76mΩ·cm² at 200A/cm² , and a high BFOM of 48.5GW/cm². In addition, the C-V characteristic and reverse recovery switch characteristic are also analyzed. In this paper, the successfully fabrication of high-voltage SiC PiN rectifier provides a further development for high-voltage high-power SiC power modules.

Abstract: Designed for 6500V 4H-SiC JBS diodes, a highly-efficient termination structure of a non-uniform multiple floating field limiting rings (MFFLR) featuring with a non-uniform ring spacing and a multiple region division is studied and purposed. For each region, ring spacing is modulated independently by a multiplication factor and a linear increment factor. The non-uniform MFFLR structure is simulated and optimized for a better electric field distribution and a higher breakdown voltage. Based on the simulation results, 4H-SiC JBS diodes with the optimized non-uniform termination designs are fabricated. Experimental results show that the SiC JBS diode with optimized non-uniform MFFLR termination structure can achieve a breakdown voltage of up to 7800 V, and its termination efficiency is about 94% of an ideal parallel-plane junction’s. Our results demonstrate that the optimized non-uniform MFFLR termination structure is capable for SiC JBS diodes with breakdown voltage of 6500V and above. Our results can provide a valuable design methodology of edge termination structures for other high-voltage SiC devices.

Abstract: In this study, the advantages of the AlN electron blocking layer (EBL) for InGaN/GaN blue light-emitting diodes (LEDs) were investigated. The LEDs with the AlN EBL exhibited better optical performance over a wide range of carrier concentration due to the suppression of electron overflow. Furthermore, the AlN EBL with a thicker last barrier layer was investigated. The thicker last barrier layer was used to enhance Electrostatic Discharge (ESD) characteristic by the better current spreading effect.