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NO Annealing Simulation of 4H-SiC/SiO₂ by Charge-Transfer Type Molecular Dynamics
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High Mobility Silicon Dioxide Layers on 4H-SiC Deposited by Means of Atomic Layer Deposition
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Temperature Dependent Mobility Model for Predictive TCAD Simulations of 4H-SiC
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Hypothesis to Explain Threshold Drift due to Dynamic Bipolar Gate Stress
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Gate Dielectric Current Transport Mechanisms in N-SiC Metal Oxide Semiconductor Capacitor
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Complications of Charge Pumping Analysis for Silicon Carbide MOSFETs
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Heavy-Ion-Induced Defects in Degraded SiC Power MOSFETs
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Physical Modelling of Charge Trapping Effects in SiC MOSFETs
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HomeMaterials Science ForumMaterials Science Forum Vol. 1090Physical Modelling of Charge Trapping Effects in...

Physical Modelling of Charge Trapping Effects in SiC MOSFETs

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Abstract:

In the recent past, lots of efforts have been put into further developing SiC power MOSFETs. In addition to optimization of device geometry, i.e., vertical device structure, various post-oxidation anneals have been studied to improve carrier mobility by reducing trap density. Nevertheless, a considerable number of traps remain, which are the central origin for dynamic changes in the threshold voltage of up to several volts during DC and AC operation. To explain the threshold voltage instability, an effective two-state defect model has been recently applied. In this work, we give an overview of modeling efforts to explain the impact of defects on the device threshold voltage and discuss the hysteresis of voltage sweep and bias temperature instabilities in SiC transistors. Based on the combination of measurements and computer simulations, a list of potential defect candidates responsible for the observed threshold voltage instabilities is discussed.

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Periodical:

Materials Science Forum (Volume 1090)

Pages:

185-191

DOI:

https://doi.org/10.4028/p-o083cb

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Cite this paper

Online since:

May 2023

Authors:

Michael Waltl*, Christian Schleich, Aleksandr Vasilev, Dominic Waldhoer, Bernhard Stampfer, Tibor Grasser

Keywords:

Bias Temperature Instabilites, Charge Trapping, Hysteresis, Interface Traps, NMP Model, Oxide Traps, Power Electronics, SiC Transistor

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Creative Commons CC BY 4.0

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* - Corresponding Author

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