Low On-Resistance in 4H-SiC RESURF JFETs Fabricated with Dry Process for Implantation Metal Mask

Takeyoshi Masuda; Kazuhiro Fujikawa; Kaoru Shibata; Hideto Tamaso; Satoshi Hatsukawa; Hitoki Tokuda; Akihiko Saegusa; Yasuo Namikawa; Hideki Hayashi

doi:10.4028/www.scientific.net/MSF.527-529.1203

Paper Titles

10 kV, 87 mΩcm² Normally-Off 4H-SiC Vertical Junction Field-Effect Transistors
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Design, Fabrication and Application of 4H-SiC Trenched-and-Implanted Vertical JFETs
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Analytical Modelling of I-V Characteristics for 4H-SiC Enhancement Mode VJFET
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Design Considerations of a New 4H-SiC Enhancement-Mode Lateral Channel Vertical JFET for Low-Loss Switching Operation
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Low On-Resistance in 4H-SiC RESURF JFETs Fabricated with Dry Process for Implantation Metal Mask
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SiC Smart Power JFET Technology for High-Temperature Applications
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Inherently Safe Resonant Reset Forward Converter Using a Bias-Enhanced SiC JFET
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Current Sensing for SiC Power Devices
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Fabrication of 700V SiC-SIT with Ultra-Low On-Resistance of 1.01mΩ•cm²
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HomeMaterials Science ForumMaterials Science Forum Vols. 527-529Low On-Resistance in 4H-SiC RESURF JFETs...

Low On-Resistance in 4H-SiC RESURF JFETs Fabricated with Dry Process for Implantation Metal Mask

Abstract:

We fabricated 4H-SiC lateral JFETs with a reduced surface field (RESURF) structure, which can prevent the concentration of electric field at the edge of the gate metal [1]. Previously, we reported on the 4H-SiC RESURF JFET with a gate length (LG) of 10 μm [2]. Its specific on-resistance was 50 mΩcm2, which was still high. Therefore, a Ti/W layer was used as an ion implantation mask so as to decrease the thickness of the mask and to improve an accuracy of the device process. A RESURF JFET with the gate length (LG) of 3.0 μm was fabricated, and the specific on-resistance of 6.3 mΩcm2 was obtained. In this paper, the fabrication process and the electrical characteristics of the device are described.