Low On-Resistance in 4H-SiC RESURF JFETs Fabricated with Dry Process for Implantation Metal Mask
We fabricated 4H-SiC lateral JFETs with a reduced surface field (RESURF) structure, which can prevent the concentration of electric field at the edge of the gate metal . Previously, we reported on the 4H-SiC RESURF JFET with a gate length (LG) of 10 μm . Its specific on-resistance was 50 mΩcm2, which was still high. Therefore, a Ti/W layer was used as an ion implantation mask so as to decrease the thickness of the mask and to improve an accuracy of the device process. A RESURF JFET with the gate length (LG) of 3.0 μm was fabricated, and the specific on-resistance of 6.3 mΩcm2 was obtained. In this paper, the fabrication process and the electrical characteristics of the device are described.
Robert P. Devaty, David J. Larkin and Stephen E. Saddow
T. Masuda et al., "Low On-Resistance in 4H-SiC RESURF JFETs Fabricated with Dry Process for Implantation Metal Mask", Materials Science Forum, Vols. 527-529, pp. 1203-1206, 2006