SiC MESFET with a Double Gate Recess

Per Åke Nilsson; Niklas Rorsman; Mattias Südow; Kristoffer Andersson; Hans Hjelmgren; Herbert Zirath

doi:10.4028/www.scientific.net/MSF.527-529.1227

Paper Titles

Inherently Safe Resonant Reset Forward Converter Using a Bias-Enhanced SiC JFET
p.1211

Current Sensing for SiC Power Devices
p.1215

Fabrication of 700V SiC-SIT with Ultra-Low On-Resistance of 1.01mΩ•cm²
p.1219

RF and DC Characterization of Self-Aligned L-Band 4H-SiC Static Induction Transistors
p.1223

SiC MESFET with a Double Gate Recess
p.1227

High Power High Efficiency Lateral Epitaxy MESFETs in Silicon Carbide
p.1231

RF Characteristics of a Fully Ion-Implanted MESFET on a Bulk Semi-Insulating 4H-SiC Substrate
p.1235

High-Frequency SiC MESFETs with Silicon Dioxide/Silicon Nitride Passivation
p.1239

Double Gate 180V-128mA/mm SiC-MESFET for Power Switch Applications
p.1243

HomeMaterials Science ForumMaterials Science Forum Vols. 527-529SiC MESFET with a Double Gate Recess

SiC MESFET with a Double Gate Recess

Abstract:

In order to increase the output power and drain efficiency, MESFETs in SiC have been made with a double gate recess technique. Typical device characteristics of the MESFETs are drain currents of 380mA/mm, breakdown voltages of 80V and ft/fmax of 10/25 GHz respectively. These transistors exhibit power densities of 3W/mm@3GHz in class AB operation and drain efficiencies of 60%. Packaged devices with 3 mm gate periphery of this type, with via-hole grounding, gave power densities of 1.2 W/mm@6GHz at 50 V drain bias.