Overlapping-Gate Architecture for Silicon Hall Bar MOSFET Devices in the Low Electron Density and High Magnetic Field Regime
A common issue in low temperature measurements of enhancement-mode metal-oxide-semiconductor (MOS) field-effect transistors (FETs) in the low electron density regime is the high contact resistance dominating the device impedance. In that case a voltage bias applied across the source and drain contact of a Hall bar MOSFET will mostly fall across the contacts (and not across the channel) and therefore magneto-transport measurements become challenging. However, from a physical point of view, the study of MOSFET nanostructures in the low electron density regime is very interesting (impurity limited mobility , carrier interactions [2,3] and spin-dependent transport ) and it is therefore important to come up with solutions [5,6] that work around the problem of a high contact resistance in such devices (c.f. Fig. 1 (a)).
B. J. Ruck and T. Kemmitt
L. H. W. Van Beveren et al., "Overlapping-Gate Architecture for Silicon Hall Bar MOSFET Devices in the Low Electron Density and High Magnetic Field Regime", Materials Science Forum, Vol. 700, pp. 93-95, 2012