Suppression of Hole Current in Graphene Transistors with N-Type Doped SiC Source/Drain Regions

Yuichi Nagahisa; Eisuke Tokumitsu

doi:10.4028/www.scientific.net/MSF.717-720.679

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HomeMaterials Science ForumMaterials Science Forum Vols. 717-720Suppression of Hole Current in Graphene...

Suppression of Hole Current in Graphene Transistors with N-Type Doped SiC Source/Drain Regions

Abstract:

To achieve graphene channel transistors which have high on/off drain current ratio and unipolar behavior of drain current – gate voltage (ID-VG) characteristics, we fabricated and characterized the top gated graphene channel transistors with n-type doped SiC source/drain regions. Graphene layer was formed on SiC by high temperature annealing in vacuum, and Al2O3 was used as a gate insulator. For the graphene channel transistor with heavily doped n-SiC source/drain regions (doping concentration ND=4.5x1019cm-3) and a 4~6ML graphene channel, ambipolar behavior was observed. On the other hand, when ND was reduced to 4.5x1018cm-3 and a thin graphene layer was used, the suppression of hole current in ID-VG curve was observed.

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Periodical:

Materials Science Forum (Volumes 717-720)

Pages:

679-682

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.717-720.679

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Online since:

May 2012

Authors:

Yuichi Nagahisa, Eisuke Tokumitsu

Keywords:

Ambipolar Behavior, Graphen, On-Off Ratio, Transistor

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