Simulation and Optimization of 4H-SiC DMOSFET Power Transistors

Chien Chung Hung; Young Shying Chen; Cheng Tyng Yen; Chwan Ying Lee; Lurng Shehng Lee; Ming Jinn Tsai

doi:10.4028/www.scientific.net/MSF.740-742.711

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Investigation of Nitrided Atomic-Layer-Deposited Oxides in 4H-SiC Capacitors and MOSFETs
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Simulation and Optimization of 4H-SiC DMOSFET Power Transistors
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HomeMaterials Science ForumMaterials Science Forum Vols. 740-742Simulation and Optimization of 4H-SiC DMOSFET...

Simulation and Optimization of 4H-SiC DMOSFET Power Transistors

Abstract:

Two-dimensional device simulations of 4H-SiC DMOSFET were performed in this study. Two types of P-Well doping profiles are compared. The retrograde profile can have higher breakdown voltage as compared to the box profiles. The P-well concentration is also examined and optimized. The DMOS device can have a better avalanche behavior once the P-Well concentration is higher than 2E18 cm-3. In addition, the interfacial oxide effect on the channel mobility has also been studied. The interfacial charge density should be controlled to lower than 2E11 cm-2 so as to have a higher mobility and lower on-state resistance.

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Periodical:

Materials Science Forum (Volumes 740-742)

Pages:

711-714

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.740-742.711

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Online since:

January 2013

Authors:

Chien Chung Hung, Young Shying Chen, Cheng Tyng Yen, Chwan Ying Lee, Lurng Shehng Lee, Ming Jinn Tsai

Keywords:

Channel Mobility, Device Simulation, DMOSFET, Silicon Carbide (SiC)

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References

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