p.3
p.11
p.15
p.21
p.27
p.33
p.39
p.45
Buffer Layer Optimization for the Growth of State of the Art 3C-SiC/Si
Abstract:
We describe a procedure for the optimization of a 3C-SiC buffer layer for the deposition of 3C-SiC on (001) Si substrates. A 100 – 150 nm thick SiC buffer was deposited after a standard carbonization at 1125 °C, while increasing the temperature from 1125 °C to 1380 °C. Ramp time influenced the quality and the crystallinity of the buffer layer and the presence of voids at the SiC/Si interface. After the optimization of the buffer, to demonstrate its effectiveness, a high-quality 3C-SiC was grown, with excellent surface morphology, crystallinity and low stress.
Info:
Periodical:
Pages:
15-19
Citation:
Online since:
October 2014
Keywords:
Price:
Сopyright:
© 2015 Trans Tech Publications Ltd. All Rights Reserved
Share:
Citation: