Metal Removal Efficiency in High Aspect Ratio Structures

Abstract:

An extremely low level of metal contamination is required for specific devices like memories and CMOS Image sensors. Most of past work in the literature has focused on blanket wafer decontamination, since metrology is mostly adapted to flat surfaces. Metal removal efficiency has been compared between blanket wafers versus high aspect ratio deep trenches wafers. Two different metrology technics enable a quantitative and spatial metal removal determination on patterned wafers. Efficient cleaning in high aspect ratio structures requires much longer cleaning recipes than on flat surfaces.

• Periodical: Solid State Phenomena (Volume 255)
• Pages: 313-318
• DOI: https://doi.org/10.4028/www.scientific.net/SSP.255.313
• Online since: September 2016
• Authors: Philippe Garnier*, Hervé Fontaine
• Keywords: CMOS Image Sensors, Deep Trenches, LPD ICPMS, Metal Removal Efficiency, SPV, VPD

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