GaN MOS Structures with Low Interface Trap Density

Rong Ming Chu

doi:10.4028/www.scientific.net/SSP.314.79

Paper Titles

Wet Chemical Cleaning of Organosilane Monolayers
p.54

Reaction Kinetics of Poly-Si Etching in TMAH Solution
p.60

Surface Chemistry and Nanoscale Wet Etching of Group IV Semiconductors in Acidic H₂O₂ Solutions
p.66

Si_1-XGe_X Selective Etchant for Gate-All-Around Transistors
p.71

GaN MOS Structures with Low Interface Trap Density
p.79

Analysis of Surface Reaction for Group III-V Compound Semiconductors in Functional Water
p.84

Effect of Surface Oxidation on the Material Loss of InGaAs in Acidic Solutions
p.89

Characterization of Wet Chemical Atomic Layer Etching of InGaAs
p.95

Highly Selective Etching between Different Oxide Films by Vapor Phase Cleaning
p.101

HomeSolid State PhenomenaSolid State Phenomena Vol. 314GaN MOS Structures with Low Interface Trap Density

GaN MOS Structures with Low Interface Trap Density

Abstract:

GaN based electronic devices have gained great success in the arena of high-frequency and high-power applications. A high-quality GaN MOS structure has the potential to enable new device designs and higher device performance, thereby bringing the success of GaN electronics to a new level. This paper discusses results of the work on GaN MOS structures show that with adequate surface preparation samples featuring interface trap density down to the ~ 10¹⁰ eV^-1cm^-2 range can be formed.

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Periodical:

Solid State Phenomena (Volume 314)

Pages:

79-83

DOI:

https://doi.org/10.4028/www.scientific.net/SSP.314.79

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Online since:

February 2021

Authors:

Rong Ming Chu*

Keywords:

Crystal Plane, Gallium Nitride, GaN, Interface Defects, MOS Characterization

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* - Corresponding Author

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