Papers by Author: Hyung Seok Lee

Abstract: Ion implantation for selective doping of SiC is problematic due to damage generation during the process and low activation of dopants. In SiC bipolar junction transistor (BJT) the junction termination extension (JTE) can be formed without ion implantation using instead a controlled etching into the epitaxial base. This etched JTE is advantageous because it eliminates ion implantation induced damage and the need for high temperature annealing. However, the dose, which is controlled by the etched base thickness and doping concentration, plays a crucial role. In order to find the optimum parameters, device simulations of different etched base thicknesses have been performed using the software Sentaurus Device. A surface passivation layer consisting of silicon dioxide, considering interface traps and fixed trapped charge, has been included in the analysis by simulations. Moreover a comparison with measured data for fabricated SiC BJTs has been performed.

Abstract: In this study, high voltage blocking (2.7 kV) implantation-free SiC Bipolar Junction Transistors with low on-state resistance (12 mΩ•cm2) and high common-emitter current gain of 50 have been fabricated. A graded base doping was implemented to provide a low resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high temperature dopant activation annealing and for avoiding generation of life-time killing defects that reduces the current gain. Also in this process large area transistors showed common-emitter current gain of 38 and open-base breakdown voltage of 2 kV.

Abstract: To determine the maximum allowed power dissipation in a power transistor, it is important to determine the relationship between junction temperature and power dissipation. This work presents a new method for measuring the junction temperature in a SiC bipolar junction transistor (BJT) that is self-heated during DC forward conduction. The method also enables extraction of the thermal resistance between junction and ambient by measurements of the junction temperature as function of DC power dissipation. The basic principle of the method is to determine the temperature dependent I-V characteristics of the transistor under pulsed conditions with negligible self-heating, and compare these results with DC measurements with self-heating. Consistent results were obtained from two independent temperature measurements using the temperature dependence of the current gain, and the temperature dependence of the base-emitter I-V characteristics, respectively.

Abstract: This paper reports a 4H-SiC bipolar junction transistor (BJT) with a breakdown voltage (BVCEO) of 1200 V, a maximum current gain (β) of 60 and the low on-resistance (Rsp_on)of 5.2 mΩcm2. The high gain is attributed to an improved surface passivation SiO2 layer which was grown in N2O ambient in a diffusion furnace. The SiC BJTs with passivation oxide grown in N2O ambient show less emitter size dependence than reference SiC BJTs, with conventional SiO2 passivation, due to a reduced surface recombination current. SiC BJT devices with an active area of 1.8 mm × 1.8 mm showed a current gain of 53 in pulsed mode and a forward voltage drop of VCE=2V at IC=15 A (JC=460 A/cm2).

Abstract: This work focuses on Ni ohmic contacts to the C-face (backside) of n-type 4H-SiC substrates. Low-resistive ohmic contacts to the wafer backside are important especially for vertical power devices. Ni contacts were deposited using E-beam evaporation and annealed at different temperatures (700-1050 °C) in RTP to obtain optimum conditions for forming low resistive ohmic contacts. Our results indicate that 1 min annealing at temperatures between 950 and 1000 °C provides high quality ohmic contacts with a contact resistivity of 2.3x10-5 Ωcm2. Also our XRD results show that different Ni silicide phases appear in this annealing temperature range.

Abstract: 4H-SiC BJTs have been fabricated with varying geometrical designs. The maximum value of the current gain was about 30 at IC=85 mA, VCE=14 V and room temperature (RT) for a 20 μm emitter width structure. A collector-emitter voltage drop VCE of 2 V at a forward collector current 55 mA (JC = 128 A/cm2) was obtained and a specific on-resistance of 15.4 m2·cm2 was extracted at RT. Optimum emitter finger widths and base-contact implant distances were derived from measurement. The temperature dependent DC I-V characteristics of the BJTs have been studied resulting in 45 % reduction of the gain and 75 % increase of the on-resistance at 225 oC compared to RT. Forward-bias stress on SiC BJTs was investigated and about 20 % reduction of the initial current gain was found after 27.5 hours. Resistive switching measurements with packaged SiC BJTs were performed showing a resistive fast turn-on with a VCE fall-time of 90 ns. The results indicate that significantly faster switching can be obtained by actively controlling the base current.

Abstract: The effect of the different types of passivation layers on the current gain of SiC BJTs has been investigated. Measurements have been compared for BJTs passivated with thermal SiO2, plasma deposited (PECVD) SiO2 and BJTs without passivation. The maximum DC current gain of BJTs with thermal SiO2 was about 62 at IC=20 mA and Vce=40 V. On the other hand, the BJTs with a passivation by PECVD SiO2 had a DC current gain of only 25. The surface recombination current was extracted from measurements with BJTs of different emitter widths. The surface recombination current of BJTs with a thermally grown oxide was about 25 % lower than unpassivated BJTs and 65 % lower than that of PECVD passivated BJTs.

Abstract: One important challenge in SiC Bipolar Junction Transistor (BJT) fabrication is to form good ohmic contacts to both n-type and p-type SiC. In this paper, we have examined contact study in a SiC BJT process with sputter deposition of titanium tungsten contacts to both n-type and p-type regions followed by annealing at different temperatures between 750 oC and 950 oC. The contacts were characterized using linear transmission line method (LTLM) structures. To see the formation of compound phases, X-ray Diffraction (XRD) θ-2θ scans were performed before and after annealing. The results indicate that 5 minutes annealing at 950 oC of the n+ contact is sufficient whereas the p+ contacts remain non-ohmic after 30 minutes annealing. The n+ emitter structure contact resistivity after 5 min annealing with 750 oC and 950 oC was 1.08 × 10-3 5cm2 and 4.08 × 10-4 5cm2, respectively. Small amorphous regions of silicon and carbon as well as titanium tungsten carbide regions were observed by high-resolution transmission electron microscopy (HRTEM), whereas less carbide formation and no amorphous regions were found in a sample with unsuccessful formation of TiW ohmic contacts.

Abstract: This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain β=64 and a breakdown voltage of 1100 V. The high β value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The current gain of the BJTs increases with increasing emitter width indicating a significant influence of surface recombination. This “emitter-size” effect is in good agreement with device simulations including recombination in interface states at the etched termination of the baseemitter junction.

Abstract: 4H-SiC BJTs were fabricated using epitaxial regrowth instead of ion implantation to form a highly doped extrinsic base layer necessary for a good base ohmic contact. A remaining p+ regrowth spacer at the edge of the base-emitter junction is proposed to explain a low current gain of 6 for the BJTs. A breakdown voltage of 1000 V was obtained for devices with Al implanted JTE.