Papers by Author: L.B. Rowland

Abstract: We report on the fabrication and testing of SiC p-i-n avalanche photodiodes. APDs of 0.25 mm2 area on a-plane (1120) 6H-SiC as well as off-axis Si face 6H and 4H-SiC were successfully fabricated. A beveled mesa was used as edge termination. Recessed windows were formed using reactive ion etching to enhance low-wavelength UV performance. We performed current-voltage tests with and without UV illumination to determine dark current, photocurrent, and gain on selected devices. Dark current was less than 1 pA at 0.5Vbr on multiple devices. Quantum efficiency of 40% or greater was observed for all orientations and polytypes.

Abstract: We present herein a first comparative analysis of the quality of 50 mm and 75 mm diameter SiC wafers, purchased directly from vendors across the world, types including the most widely available configurations. Large Area White Beam Synchrotron Back Reflection X-Ray Topography was used to analyse selected ~1cm2 regions at various locations on up to 10 different bulk SiC wafers. The study concentrated particularly on the density and distribution of threading screw dislocations (TSDs). We also examined all wafers for basal plane dislocation (BPDs) densities and distributions. Alarmingly large variation in wafer quality was observed. TSD densities vary from a minimum of 0 cm-2 (in a-plane material) to values as large as over 2,000 cm-2 on some n-type 4H-SiC wafers. TSD densities on individual wafers can also vary by similar magnitudes, e.g. 500cm-2 to 2,500 cm-2 on two regions only 2 cm apart on a 50 mm diameter wafer. Computer-based image process analysis was used to present a statistical analysis of the distributions of defects. For example algorithms created in MATLAB®, Image Processing Toolbox, isolated possible TSD locations allowing rapid counting to be performed. These counts were confirmed by manual counting of selected unmodified images.

Abstract: Cold-wall vapor phase epitaxy was utilized to grow uniform 4H-SiC layers with abrupt doping interfaces on 4o off-axis substrates. Concentrations of Al were reduced roughly 200x after 0.1 μm of epitaxy after trimethylaluminum flow was stopped. Thickness uniformity of cold-wall epitaxy across 3” wafers was as good as 3.2%. Minority carrier diffusion lengths of 27 μm-thick 4H-SiC epitaxy grown in a cold-wall design were as high as 58 μm.

Abstract: Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).