Papers by Author: Thierry Conard

Abstract: The steam oxidation of SiGe shows a transition from Si-like to Ge-like oxidation behavior depending on Ge concentration and oxidation temperature. Ge-like oxidation is described by the generation of oxygen vacancies (VO) at the interface between the oxide and SiGe virtual substrate. [1] Due to the different oxidation behavior, the presence of a Ge-oxide-free interfacial layer (IL) can suppress SiGe oxidation. [2] Here we show how a passivating interfacial layer can be grown using low-pressure oxidation and highlight the importance of SiGe surface preparation prior to low-pressure oxidation.

Abstract: In this study of nanoscale etching for state-of-the-art device technology the importance of the nature of the surface oxide, is demonstrated for two III-V materials. Etching kinetics for GaAs and InP in acidic solutions of hydrogen peroxide are strikingly different. GaAs etches much faster, while the dependence of the etch rate on the H⁺ concentration differs markedly for the two semiconductors. Surface analysis techniques provided information on the surface composition after etching: strongly non-stoichiometric porous (hydr)oxides on GaAs and a thin stoichiometric oxide that forms a blocking layer on InP. Reaction schemes are provided that allow one to understand the results, in particular the important difference in etch rate and the contrasting role of chloride in the dissolution of the two semiconductors.

Abstract: In this work, the compatibility of InP and InGaAs in cleaning solutions commonly used in semiconductor manufacturing is investigated. Aqueous oxidizing cleans should be avoided as the substrates dissolve rapidly. Low pH solutions may impose some serious ES&H issues due to hydride evolution occurring upon acidic hydrolysis of the III-V material. However, acidic solutions are very efficient to remove the native oxide from the substrate. Complete oxide free surfaces are not achieved after wet cleaning due to the rapid oxidation of these materials in the atmosphere.

Abstract: Since silicon will ultimately face physical limitations, germanium and III-V materials, such as Ga, GaAs, InGaAs, are being extensively investigated for their high electron and hole mobility advantages. Prior to implementing germanium or III-V materials, it is believed that SiGe with high Ge concentration will be applied for channel materials in pMOS devices with high-k and metal gates in order to simultaneously adjust the work function and to increase the hole mobility. However, introduction of new channel materials leads to new challenges and substantial changes in the FEOL process flow.