Papers by Keyword: Carbon Face

Abstract: 4H-SiC(000-1) C-face was oxidized in H₂O and H₂ mixture gas (H₂ rich wet ambient) for the first time. H₂ rich wet ambient was formed by the catalytic water vapor generator (WVG) system, where the catalytic action instantaneously enhances the reactivity between H₂ and O₂ to produce H₂O. The dependence of SiC oxidation rate on the H₂O partial pressure was investigated. We fabricated 4H-SiC C-face MOS capacitor and MOSFET by the H₂ rich wet re-oxidation following the dry O₂ oxidation. The density of interface traps was reduced and the channel mobility was improved in comparison with the conventional O₂ rich wet oxidation.

Abstract: Metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) were fabricated on C-face 4H-SiC with post-oxidation annealing in phosphorus- containing atmosphere. POCl3/N2 annealing at 1000 °C, which is an effective condition for Si-face, did not bring any improvement in the interface state density (Dit) for C-face due to additional oxide growth. We have developed a new process sequence suitable for C-face MOS structures. As a result, the Dit near the conduction band edge was drastically decreased by the developed process to less than 3x1011 cm−2eV−1. The field-effect mobility of C-face 4H-SiC MOSFETs was effectively increased to 37 cm2/Vs. We found that the incorporation of phosphorus atoms into the SiO2/SiC interface can improve MOSFET performance not only for the Si-face but also for the C-face.

Abstract: The gate oxide reliability and channel mobility of carbon face (000-1) 4H Silicon Carbide (SiC) MOSFETs are investigated. Several gate oxidation processes including dry oxygen, pyrogenic steam, and nitrided oxides were investigated utilizing MOS capacitors for time dependent dielectric breakdown (TDDB), dielectric field strength, and MOSFETs for inversion layer mobility measurements. The results show the C-face can achieve reliability similar to the Si-face, however this is highly dependent on the gate oxide process. The reliability is inversely related to the field effect mobility where other research groups report that pyrogenic steam yields the highest electron mobility while this work shows it has weakest oxide in terms of dielectric strength and shortest time to failure.

Abstract: UMOSFET is theoretically suitable to decrease the on-resistance of the MOSFET. In this study, in order to determine the cell structure of the SiC UMOSFET with extremely low on-resistance, influences of the orientation of the trench and the off-angle of the wafer on the MOS properties are investigated. The channel resistance, gate I-V curves and instability of threshold voltage are superior on the {11-20} planes as compared with other planes. On the vicinal off wafer, influence of the off-angle disappears and the properties on the equivalent planes are almost the same. The obtained results indicate that the extremely low on-resistance with the high stability and high reliability is possible in the SiC UMOSFET by the hexagonal cell composed of the six {11-20} planes on the vicinal off wafer, and actually an extremely low channel resistance was demonstrated on the hexagonal UMOSFET with the six {11-20} planes on the vicinal off wafer.

Abstract: Silicon carbide Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The DIMOSFETs were characterized from room temperature to 250°C. At room temperature, they showed a specific on-resistance of 4.9 mΩcm2 at a gate bias of 20 V and a drain voltage of 1.0 V. The specific on-resistance taken at a drain current (Id) of 260 A/cm2 was 5.0 mΩcm2. The blocking voltage of this device was higher than 1360 V at room temperature. At 250°C, the specific on-resistance increased from 5.0 mΩcm2 to 12.5 mΩcm2 and the threshold voltage determined at Id = 26 mA/cm2 decreased from 5.5 V to 4.3 V.

Abstract: It is known that a Schottky barrier height (b) of metal/C-face 4H-SiC Schottky barrier diode (SBD) differ from b of metal/Si-face 4H-SiC SBD. Furthermore, b of metal/4H-SiC SBD varies with annealing temperature. We fabricate 0.231mm2 SBD with Ti/SiC interface using Si-face and C-face 4H-SiC. These SBDs are annealed at several temperatures after a formation of the Ti/SiC interface. As a result, b of Ti/C-face 4H-SiC interface annealed at 400 oC is nearly equal to b of Ti/Si-face 4H-SiC interface annealed at 500 oC and the n-values of these SBDs are nearly equal to the ideal value (unity). Using that annealing condition, we fabricated 25mm2 junction barrier Schottky (JBS) diodes with Ti/SiC interface on Si-face and C-face 4H-SiC epitaxial substrate. b of Si-face and C-face JBS diodes are 1.26eV and 1.24eV, respectively. The leakage currents for both Si-face and C-face JBS diodes are less than 1mA/cm2. The current of 100A is obtained at the forward bias voltage of 1.95V and 2.16V for the Si-face JBS and the C-face JBS.

Abstract: Characteristics of metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated by direct oxidation of C-face 4H-SiC in NO were investigated. It was found that nitridation of the C-face 4H-SiC MOS interface generates near-interface traps (NITs) in the oxide. These traps capture channel mobile electrons and degrade the performance of MOSFETs. The NITs can be reduced by unloading the samples at room temperature after oxidation. It is important to reduce not only the interface states but also the NITs to fabricate high-performance C-face 4H-SiC MOSFETs with nitrided gate oxide.

Abstract: This research is focused on the influence of high C/Si ratios and low pressure on n-type doping concentration and surface defects of 4H-SiC C-face epilayers. N-type doping concentration decreases as C/Si ratio increases from 3.0 to 4.0 and pressure reduces from 100 mbar to 50 mbar; defect densities decrease as pressure increases at both C/Si ratios of 3.0 and 4.0. RMS roughness is about 0.21 nm for all C-face samples, independent of C/Si ratios of 3.0 and 4.0 and pressure from 50 mbar to 100 mbar. However, the influence of growth temperature on doping concentration and surface defects can not be clearly observed in this work.

Abstract: The oxide reliability of metal-oxide-semiconductor (MOS) capacitors on 4H-SiC(000-1) carbon face was investigated. The gate oxide was fabricated by using N2O nitridation. The effective conduction band offset (Ec) of MOS structure fabricated by N2O nitridation was increased to 2.2 eV compared with Ec = 1.7 eV for pyrogenic oxidation sample of. Furthermore, significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. It is suggested that the N2O nitridation as a method of gate oxide fabrication satisfies oxide reliability on 4H-SiC(000-1) carbon face MOSFETs.

Abstract: Reliability of the gate oxide is influenced by the device structure and the processes. In the SiC MOSFET, the surface morphology is degraded by the high temperature activation RTA, and the degradation is remarkable on the n+ source region. This study develops the method to suppress the degradation of the reliability of the gate oxide on the carbon face. By utilizing the carbon cap for the RTA and the high density O2 plasma etching to remove the carbon cap, the reliability is drastically improved both on the un-implanted and the implanted surfaces. Especially, the degradation of the reliability is perfectly suppressed on the un-implanted surface.