Design of a 30 nm Germanium FinFET by Parameter Optimization

Abstract:

Germanium (Ge) is envisioned as a suitable channel candidate for field-effect transistors (FET). Properties of Ge such as high carrier mobility, compatibility with Si and adaptability with high-k materials makes it comparable to silicon. This paper presents a detailed design of a 30 nm Ge based FinFET by parameter optimization using Silvaco software. Poisson and Schrodinger equation is used to come up with an analytical quantum model. The quantum model is developed based on theory of a double gate (DG) FET but the final design is a trigate (TG) device since they are more scalable. The quantum attributes of DG MOSFET are acquired by adopting the coupled Poisson–Schrodinger equation with the aid of the variational approach. The ratio of channel length (L_C) to fin height (H_fin) to fin thickness (t_fin) is 4:2:1. The channel length is taken as the gate length (L_G) although they are slightly differ mathematically due to side diffusion of the implanted ions. Simulation results show that physical parameters such as dimensions influence electrical characteristics of the device such as threshold voltage (V_TH). Much focus is on optimization of the on/off current ratio (I_ON/_OFF) and V_TH performances. I_ON/_OFF ≈ 10⁶ is achieved at carrier concentration in the range 1 × 10¹⁸ ≤ n_d ≤ 1.22 × 10¹⁸ and in this scenario, V_TH = 0.4V . Systematical investigation is presented using IV characteristics to demonstrate the sensitivity or how critical design parameters of Ge FinFET are to the device’s figure of merits. Device performs well at low voltages but breaks down at higher drain voltages (V_DS ≥ 4V). Gate source voltages (V_GS) range between 0.05V≤ V_GS ≤ 1V and conductance is dependent on it. Effects of DIBL, which is around 0.031, and velocity saturation are studied to determine how they can be suppressed during the design process.

• Periodical: Advanced Engineering Forum (Volume 44)
• Pages: 105-118
• DOI: https://doi.org/10.4028/www.scientific.net/AEF.44.105
• Online since: January 2022
• Authors: Gofaone Mogosetso, Caspar Lebekwe, Nonofo M.J. Ditshego*
• Keywords: Doping, Drain Current, Drain Voltage, FinFET, Gate Oxide Thickness, Nano, On/Off Current Ratio, QMEs, SCEs, Threshold Voltage

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