Applied Mechanics and Materials Vols. 380-384

Abstract: The interference from UHVDC power lines is a key issue puzzling the geo-electric field observation in seismic station. According to the working principle of geo-electric field observation instrument, the interference reason on geo-electric field observation is analyzed, which potential distribution of the electrodes in soil of geo-electric field observation instrument is changed by the ground current from ground electrode of power line. Based on the different electrode arrangements, the electric field calculation model at different positions away from ground electrode is established, and thus the variation could be acquired. The results show that interference values are affected due to the electrode spans and the electrode arrangement directions, and there has the minimum interference when the electrode span is 100 m or the angle between line of two electrodes and radial line of ground electrode is 45°.

Abstract: According to the demand of low voltage ride through (LVRT) in China, the operation features of DFIG during grid fault are analyzed. A new topology combining SVC with a novel DVR is put forward in this paper. The problems such as slow voltage recovery in early time of the grid fault and over compensation of voltage in the later time of the fault are overcome. The over current in rotor side of DFIG during the grid fault is restricted at the same time. The simulation model for the new topology is built in MATLAB/Simulink. The effectiveness of the topology in improving the ability of LVRT is verified.

Abstract: A stability control technique for load modeling is proposed in AC/DC hybrid transmission system. A frequency-dependent mult-infeed HVDC system matrix is obtained accurately via the complex curve fitting technique. With the mult-infeed HVDC system matrix the mutual coupling effect is included in the synthesis procedure automatically, resulting in a great effect on improving load model precision and adaptability.

Abstract: An rail-to-rail operational amplifier is presented in this paper, which is designed by with two op amp, the first level of the structure is the complementary differential structure which will providing input for the operational amplifier, the second level is designed with the structure of folding cascode to get a high gain. The operational amplifier is designed with the TSMC 0.35u m3.3VCMOS mixed analog-digital technology library. The simulated results show that the operational amplifier has a DC gain of 110dB,a GBW of 9.5MHz,a static power dissipation of 0.95mW,a phase margin of 73°,a voltage slew rate of 8.2V/μS,an input and output range of 0-3.3V,when operating at 3.3V power supply and a 20pF output load.

Abstract: An embedded microprocessor core used for ASIC is presented, which is compatible with 6502 microprocessor. Simulation shows that the timing sequence of the circuit meets the requirement of 6502 microprocessor. The device features high speed and low power consumption.

Abstract: A low voltage, low power two-stage operational amplifier (op-amp) was proposed in this paper. A folded-cascode structure is used in the input stage of the amplifier to get high gain. Current mirrors are used in the input stage to make the transconduotance constant. A simple push-pull common source amplifier is adopted as the output stage to take the advantages of its high efficiency. The experimental results show that the unity-gain bandwidth is 12.5MHz, the low-frequency open-loop voltage gain is 100dB,the phase margin is 65°, and power dissipation is 98.8μw.

Abstract: A fully integrated low noise amplifier (LNA) for wireless local area network (WLAN) application is presents. The circuit is fabricated in 0.18μm SiGe BiCMOS technology. For the low noise figure, a feedback path is introduced into the traditional inductively degenerated common emitter cascade LNA, which decreases the inductance for input impedance matching, therefore reduces the thermal noise caused by loss resistor. Impedance matching and noise matching are achieved at the same time. Measured results show that the resonance point of the output resonance network shifts from 2.4GHz to 2.8GHz, due to the parasitic effects at the output. At the frequency of 2.8GHz, the LNA achieves 2.2dB noise figure, 19.4dB power gain. The core circuit consumes only 13mW from a 1.8V supply and occupies less than 0.5mm².

Abstract: Based on direct digital frequency synthesizer ( DDS ) of the working principle, designfunction signal generator based on FPGA chip as the core, the application of Verilog language andQuartus II provided by software schematic design function, completed a system circuit design, using Modelsim on the circuit in the simulation, the simulation results are analyzed, the validationof the design method for the reliability and feasibility.

Abstract: SOPC technology of Nios II is Used for the design of intelligent digital photo frame in this paper. Developers can integrate design according to actual needs, fundamentally changing the lack of traditional design. Digital photo frame as a whole project is divided into two parts of the hardware module and software system. Functional correctness is verified by Quartus II, further downloaded to the FPGA for debugging, the observation results showed that digital photo frame has a high degree of freedom in the system optimization, which can be extended the life of the product on the market, greatly improving the performance of multi-function digital photo frame.

Abstract: This paper presents a photoelectric detection circuit for microfluidics chip. The proposed photoelectric detection system can reduce noise and increase sensitivity. It is consist of pre-amplifier, ac-amplifier and band-pass filter. The transfer function of photoelectric detection circuit is introduced. The circuit implementations and simulation results are given. The proposed photoelectric detection circuit is suitable for integrated microfluidics chip.